XPS: CLCCA: Enhancing the Programmability of Heterogeneous Manycore Systems

随着计算设备被用于解决日益复杂和多样化的问题以及不断增加的多维数据集，程序员的任务是编写高性能和节能的代码。为了运行这些代码，处理器供应商正在采用异构系统，在这些系统中，传统的通用核心与图形处理单元（gpu）、加密加速器、数据库加速器和视频编码器/解码器等加速器集成在一起。为了确保这些系统的广泛采用，它们的编程模型必须是有效且易于使用的。不幸的是，这些系统的当前编程模型具有挑战性，要求程序员显式地在内核和加速器之间来回分配、管理和编组内存。因此，软件经常容易出错和有bug，并且遭受数据复制和移动的开销。随着未来的系统包含越来越多的异质性，这个问题将会恶化。该方案为核心和加速器开发了统一的地址空间，这是一个有效的编程模型的关键部分。统一的地址空间（包括虚拟地址和物理地址）增加了系统的可编程性，因为：(1)程序员不需要手动分配和管理数百个异构计算单元之间的数据移动；(2)系统在执行转移时自动分配、复制和迁移异构组件之间的数据；(3)这些系统支持需要核心和加速器同时访问公共数据结构的新算法（例如，cpu和gpu通过软件任务队列通信的生产者-消费者程序）；(4)程序现在更易于在具有可选内存层次结构的系统之间移植。这项工作通过开发新的硬件（例如，新的内存控制器，Translation Lookaside Buffer增强，关机机制）和操作系统（OS）支持（例如，新的OS内存分配机制和对异构系统和内存上的页面分配、复制和迁移的支持）来研究支持这些好处的机制（同时保持高性能和低功耗）。

As computing devices are used to solve increasingly complex and diverse problems with ever-increasing multidimensional data-sets, programmers are tasked with writing high-performance and energy-efficient code. To run this code, processor vendors are adopting heterogeneous systems, where conventional general-purpose cores are integrated with accelerators like graphics processing units (GPUs), cryptographic accelerators, database accelerators, and video encoders/decoders. To ensure the widespread adoption of these systems, it is essential that their programming models are effective and easy to use. Unfortunately, current programming models for these systems are challenging, requiring the programmer to explicitly allocate, manage, and marshal memory back and forth between cores and accelerators. As a result, software is often error-prone and buggy, and suffers overheads from data replication and movement. As future systems incorporate increasing levels of heterogeneity, this problem will worsen.This proposal develops unified address spaces for cores and accelerators, which is a key part of an effective programming model. A unified address space (in both virtual and physical addresses) increases system programmability because: (1) programmers need not manually allocate and manage their data movement between hundreds of heterogeneous compute units; (2) the system automatically allocates, replicates, and migrates data among heterogeneous components as execution shifts; (3) these systems support new algorithms that require simultaneous core and accelerator access to common data structures (e.g., producer-consumer programs where CPUs and GPUs communicate through software task queues); (4) programs are now more portable across systems with alternate memory hierarchies. This work studies mechanisms to support these benefits (while maintaining high performance and low power) by developing novel hardware (e.g., new memory controllers, Translation Lookaside Buffer augmentations, shootdown mechanisms) and operating system (OS) support (e.g., new OS memory allocation mechanisms and support for page allocation, replication, and migration on heterogeneous systems and memory).