CAREER:Cross-Core Learning in Future Manycore Systems

随着计算设备解决越来越复杂和多样化的问题，工程师们寻求设计出提供更高性能的处理器，同时出于环境原因保持节能。为了实现这一目标，处理器供应商已经采用了多核设备，其中数千个核心在单个芯片上协作，以并行方式解决大规模问题。他们进一步整合了异构性，在单个芯片上结合不同架构的核心，以提供不断提高的每瓦性能。该项目通过发明新颖的跨核心学习技术，促进了对更高能效性能的探索。为了在将来更有效地运行程序，当前芯片中的核心单独学习并行程序的行为，为此投入了复杂且耗电的硬件结构。然而，本研究发现，并行程序倾向于以相关的方式运行不同内核的硬件结构，这意味着在一个内核上运行的程序的行为可以传达给其他内核，以获得各种性能和功耗优势。因此，这种形式的智能跨核心信息交换在实现从数据中心到嵌入式系统的跨计算领域的每瓦特高性能方面是有效的。因此，本研究提供了推断并行程序的各种线程如何相似地使用其核心的硬件结构的技术（查看一系列不同的程序员、编译器和体系结构机制来实现这一点）。当检测到这种情况时，跨核学习硬件收集最有用的信息来交换以提高性能或功率，然后使用低开销的硬件/软件技术在异构核之间传输此信息。这个项目开发了一个轻量级的运行时软件层来编排这种信息交换，必要时依赖于专用的硬件支持。通过开发这个框架，跨核学习被应用于许多特定的情况，从更高性能的多核缓存预取和分支预测，到横向扩展系统中中断和异常的性能和电源管理技术，以及线程和指令调度。此外，该项目通过积极的研究和课程作业，让研究生、本科生和高中学生参与进来，大量传播有关如何设计和编程大规模多核系统（或向外扩展系统）的知识。总的来说，这项工作通过以下方式影响工程界和更广泛的社会：(1)帮助实现高性能，节能和环保的计算系统；(2)为学者和芯片设计师提供研究多核设计的设计方法和基础设施；(3)扩大弱势群体在计算机科学领域的参与；(4)对研究生、本科生和高中生进行多核系统并行编程教育。

As computing devices solve increasingly complex and diverse problems, engineers seek to design processors that provide higher performance, while remaining energy-efficient for environmental reasons. To achieve this, processor vendors have embraced manycore devices, where thousands of cores cooperate on a single chip to solve large-scale problems in a parallel manner. They have further incorporated heterogeneity, combining cores with different architectures on a single chip in a bid to provide ever-increasing performance per watt. This project boosts the search for higher energy-efficient performance by inventing novel cross-core learning techniques. Cores in current chips individually learn about the behavior of parallel programs in order to run programs more efficiently in the future, devoting complex and power-hungry hardware structures to do this. However, this research observes that parallel programs tend to exercise the hardware structures of different cores in correlated ways, meaning that the behavior of the program run on one core can be communicated to other cores for various performance and power benefits. As such, this form of intelligent cross-core information exchange is effective in achieving high performance per watt across computing domains from datacenters to embedded systemsIn this light, this research provides techniques to deduce how similarly a parallel program's various threads exercise their cores' hardware structures (looking at a range of different programmer, compiler, and architectural mechanisms to do so). When this is detected, cross-core learning hardware gleans the information that is most useful to exchange to improve performance or power, and then transmits this information among heterogeneous cores using low-overhead hardware/software techniques. This project develops a lightweight runtime software layer to orchestrate this information exchange, relying on dedicated hardware support when necessary. Through developing this framework, cross-core learning is applied to a number of specific cases, ranging from higher-performance manycore cache prefetching and branch prediction, to performance and power-management techniques for interrupts and exceptions in scale-out systems, as well as thread and instruction scheduling. Furthermore, this project heavily disseminates knowledge on how to design and program large-scale manycore systems (or scale-out systems) by involving students at the graduate, undergraduate, and high-school levels through active research and coursework. Overall, this work impacts the engineering community and broader society by: (1) helping to achieve high-performance, but also energy-efficient and environmentally-friendly computing systems; (2) providing academics and chip designers a design methodology and infrastructure to study manycore design; (3) broadening the participation of underrepresented groups in computer science; (4) educating graduate, undergraduate, and high-school students on parallel programming for manycore systems.