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SHF: Small: Heterogeneous Memory Architectures for Future Many-core Systems

SHF: Small: Heterogeneous Memory Architectures for Future Many-core Systems
SHF:小型:未来多核系统的异构内存架构
批准号:
1218794
负责人:
Abhishek Bhattacharjee
金额:
$15.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2012
资助国家:
美国
项目状态:
已结题
起止时间:
2012-07-01 至 2015-06-30

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中文摘要
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英文摘要
As computation devices are becoming increasingly ubiquitous, they are running software from a variety of domains ranging from the mobile and graphics space all the way to high-performance, large-data server domains. This software must achieve high performance, while consuming minimal power for environmental reasons. As a result, computing systems are becoming increasingly heterogeneous, accommodating diverse hardware structures conducive to different software domains on a single platform. While processors in computing systems have traditionally been the focal point for this proliferation of heterogeneity, memory systems continue to be architected using traditional means. As such, a major challenge in forward-looking heterogeneous computing systems is how best to design memory systems to support this heterogeneity. These designs are crucial to ensure that computing systems continue to adapt to their varied software, performance, and energy requirements.This research provides the foundation to construct memory systems using a variety of architectures and technologies to run software from a variety of domains in a high-performance, yet energy-efficient manner. This work focuses on (1) constructing a systematic design methodology, software characterizations, and analytical models that guide how diverse current and future memory technologies should be combined to best support heterogeneous computing systems software, and (2) designing a range of detailed, yet flexible experimental platforms to test such studies. This project impacts society in a number of ways, most keenly by (1) reducing the energy consumption of current and future heterogeneous computing systems without sacrificing their high performance; (2) providing a systematic and rigorous scientific means to match different memory technologies and components to different software requirements; and (3) creating the evaluation tools necessary to accommodate a host of future memory subsystem research.
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