GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for Broadband Applications

点击翻译按钮获取中文摘要

Proposal No:1404890GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for RF-to-Digital Applications That Digitize Up to 1 GHz Bandwidth with Low Power ConsumptionJose Silva-MartinezTexas A&M UniversityAbstract:This project promises to improve the power efficiency, bandwidth and resolution of real-world analog signals with processing made possible by the development of a novel analog-to-digital converter with an unmatched architecture that will have a significant impact on extending the battery lifetime and reliability of electronic devices, and it also has the potential to reduce the production cost of mixed-mode systems on chips. Currently more than 2.7 billion users demand a global network capacity of several trillions of bits per second. Smaller feature size transistors in CMOS technology allow more digital functions in a single chip making possible the physical realization of more complex signal processing algorithms that were prohibited in the recent past. The "All in One" mobile systems are clearly becoming the preferred source of communication. For instance, emerging Long-Term Evolution (LTE) standards for the next generation of cellular phones have been developed to allocate more and faster services. Applications such as entire digitization of the newly deployed digital TV channels, high resolution image recognition as well as a number of military applications require wide-band and high resolution digitizers, usually requiring over 12 effective number of bits. This project is a step towards the digitization of multiple services. Consumer electronics, wireless communication and image processing industries as well as homeland security and military sectors will benefit from the development of high-resolution broadband real-time digitizers.This project is designed to meet future multi-standard application demands with a new highly efficient, high-resolution analog-to-digital converter (ADC) operating in the GHz frequency range. The aim of this project is to develop an ADC architecture that digitizes up to 1 GHz bandwidth with modest power consumption, utilizing minimal digital resources. The proposed time interleave ADC architecture will employ four pipeline sub-ADCs, running at 500 MS/s each to achieve a resolution of 12 effective number of bits at a rate of 2x109 signal samples per second while overall power dissipation is under 500mWatts. This will be possible by leveraging a very fast (40 nm or more) CMOS technology, developing an efficient calibration scheme for better linearity and integrating innovative IC design techniques suitable for high-resolution low-power broadband applications. The input signal is processed by four independent channels that operate in parallel, which then relaxes the requirements for every channel. The main drawback of this approach is the fact that system linearity, and so system performance, is limited by unavoidable mismatches between channels. Inaccuracies when sampling the input signal represents another relevant limitation to system resolution. This research will develop innovative solutions to resolve these existing hurdles and will focus on combining the calibration schemes with through limited-gain but highly-linear amplification stages that should result in greener solutions. High-gain amplifiers will be avoided when possible since they are power hungry and their bandwidth is limited. A new efficient residue curve will be used to further improve sub-ADCs linearity and reduce system power consumption. The proposed architecture is a relevant step towards the realization of efficient RF-to-digital information converters, minimizing the use of noisy and inaccurate analog hardware.