SHF: Small: Automatic High-Level Synthesis of Approximate Computing Circuits

SHF：小型：近似计算电路的自动高级综合

• 批准号: 1420864
• 负责人: Sherief Reda
• 金额: $ 45万
• 依托单位: Brown University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-07-01 至 2018-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1420864&HistoricalAwards=false
• 关键词: SHF; Small; Automatic; Level; Synthesis

Reducing the power consumption of computing devices is a highly desirable goal for modern digital circuits. This project seeks new methods to lower power consumption of digital circuits by exploiting the inherent error resiliency of emerging application domains such as signal and image processing, computer vision, and machine learning. By giving up some arithmetic accuracy, it is possible to design approximate circuits with dramatically lower power consumption and smaller silicon footprint. Low-power and reliable operation of computing systems is key for the continued push for smaller, faster and increased functionality for these systems. Other than the obvious technical impact to industry, broader impacts of this project would include new and existing course development and development of a technical workforce, as it will involve a number of graduate and undergraduate students.This project investigates new methods for the synthesis of approximate circuits that will be generated directly from their high-level behavioral descriptions. Working directly from high-level behavioral descriptions gives larger leverage for approximate circuit generation and easier incorporation within standard design flows. The novel synthesis approach is inspired by program analysis techniques used in software engineering. The PIs propose: (1) techniques for intelligent analysis of hardware designs to produce approximate circuits where designers can trade-off power and accuracy in a controlled fashion; (2) techniques that enable fast and efficient design space exploration of approximate computing designs; and (3) support circuitry that leads to low-area overhead for either low-power or error-resilient deployments. This project will result in a software tool that will fit within standard integrated circuit design flows, and will take as input a system accurately described in a behavioral hardware description language and will produce as an output approximate computing circuits along with their support circuitry. The tool will enable designers to make appropriate tradeoff decisions between arithmetic accuracy, power consumption, error resiliency and hardware overhead.

降低计算设备的功耗是现代数字电路的高度期望的目标。该项目旨在通过利用新兴应用领域（如信号和图像处理，计算机视觉和机器学习）的固有错误弹性来降低数字电路的功耗。通过放弃一些算术精度，可以设计出功耗显著降低、硅占用面积更小的近似电路。计算系统的低功耗和可靠运行是持续推动这些系统更小、更快和更强功能的关键。除了对工业的明显技术影响外，该项目更广泛的影响将包括新的和现有的课程开发和技术劳动力的发展，因为它将涉及一些研究生和本科生。该项目研究了直接从其高级行为描述中生成的近似电路合成的新方法。直接从高层次的行为描述工作，为近似电路生成提供了更大的杠杆作用，并更容易纳入标准设计流程。 新的综合方法的灵感来自软件工程中使用的程序分析技术。PI建议：（1）用于硬件设计的智能分析以产生设计者可以以受控方式权衡功率和精度的近似电路的技术;（2）实现近似计算设计的快速和高效设计空间探索的技术;以及（3）支持导致低功率或错误恢复部署的低面积开销的电路。这个项目将导致一个软件工具，将符合标准的集成电路设计流程，并将作为输入一个系统准确描述的行为硬件描述语言，并将产生作为输出近似计算电路沿着与他们的支持电路。 该工具将使设计人员能够在算法精度、功耗、错误恢复能力和硬件开销之间做出适当的权衡决定。