SHF: Small: Automatic High-Level Synthesis of Approximate Computing Circuits

降低计算设备的功耗是现代数字电路非常理想的目标。该项目寻求新的方法，通过利用新兴应用领域如信号和图像处理、计算机视觉和机器学习的固有错误恢复能力来降低数字电路的功耗。通过放弃一些算术精度，就有可能设计出功耗极低、硅占地面积更小的近似电路。计算系统的低功率和可靠运行是继续推动这些系统的更小、更快和更多功能的关键。除了对工业的明显技术影响，该项目的更广泛的影响将包括新的和现有的课程开发和技术劳动力的发展，因为它将涉及许多研究生和本科生。该项目研究将从其高级行为描述直接生成的近似电路的新方法。直接从高级行为描述进行工作可以更好地利用近似电路生成，并更容易融入标准设计流程。这种新的综合方法的灵感来自于软件工程中使用的程序分析技术。PI建议：(1)智能分析硬件设计以产生近似电路的技术，其中设计者可以在受控的方式中权衡功率和精度；(2)支持快速高效地探索近似计算设计的设计空间的技术；以及(3)支持导致低功率或容错部署的低面积开销的电路。这个项目将产生一个符合标准集成电路设计流程的软件工具，并将以行为硬件描述语言准确描述的系统作为输入，并将产生近似计算电路及其支持电路作为输出。该工具将使设计人员能够在算术精度、功耗、错误恢复能力和硬件开销之间做出适当的权衡决定。

Reducing the power consumption of computing devices is a highly desirable goal for modern digital circuits. This project seeks new methods to lower power consumption of digital circuits by exploiting the inherent error resiliency of emerging application domains such as signal and image processing, computer vision, and machine learning. By giving up some arithmetic accuracy, it is possible to design approximate circuits with dramatically lower power consumption and smaller silicon footprint. Low-power and reliable operation of computing systems is key for the continued push for smaller, faster and increased functionality for these systems. Other than the obvious technical impact to industry, broader impacts of this project would include new and existing course development and development of a technical workforce, as it will involve a number of graduate and undergraduate students.This project investigates new methods for the synthesis of approximate circuits that will be generated directly from their high-level behavioral descriptions. Working directly from high-level behavioral descriptions gives larger leverage for approximate circuit generation and easier incorporation within standard design flows. The novel synthesis approach is inspired by program analysis techniques used in software engineering. The PIs propose: (1) techniques for intelligent analysis of hardware designs to produce approximate circuits where designers can trade-off power and accuracy in a controlled fashion; (2) techniques that enable fast and efficient design space exploration of approximate computing designs; and (3) support circuitry that leads to low-area overhead for either low-power or error-resilient deployments. This project will result in a software tool that will fit within standard integrated circuit design flows, and will take as input a system accurately described in a behavioral hardware description language and will produce as an output approximate computing circuits along with their support circuitry. The tool will enable designers to make appropriate tradeoff decisions between arithmetic accuracy, power consumption, error resiliency and hardware overhead.