SHF: Small: Automatic Generation of Cache Coherent Memory Systems for Multicore Processors

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Today’s computer processors are called multicore processors, because they have multiple processor cores in them, all of which can be working simultaneously on computational tasks. These cores share data with each other using a communication protocol called cache coherence, which ensures that the data used by these cores is up-to-date and correct. Cache coherence protocols are notoriously complicated and difficult to design, and they are at least as difficult to then verify as being correct in all situations. Because of their complexity, coherence protocols take a large and disproportionate share of the design and verification resources when the computer industry creates a new processor. Furthermore, the difficulty of designing coherence protocols is increasing as processor cores scale up in variety and number on a single chip. This project is developing a novel tool that enables computer architects to quickly and easily design high-performance coherence protocols that are provably correct. The tool has the potential to radically change the way that protocols are designed, in both industry and academia, and thus make processor design faster, cheaper, and more reliable. Through an outreach program and a research fellowship program for undergraduates, the project will benefit from the contributions of women, under-represented populations, and undergraduate researchers.As processor designs change--with the addition of more cores or different types of cores, or with different expected communication patterns--there are incentives to create new coherence protocols to suit these changes. Even if a new protocol is not a radical departure from previous protocols, designing it and validating it are arduous, bug-prone processes.This project is developing a novel tool, called ProtoGen+, for automating the design of verifiable cache coherence protocols. The architects need only provide simplified protocol designs that omit complexity like hierarchy and concurrent communications. The tool takes those simplified protocol designs and automatically generates the high-performance versions of those protocols, thus hiding the complexity from the architects. ProtoGen+ then outputs the complicated, concurrent protocol. ProtoGen+ greatly reduces design and verification effort and minimizes the number of design bugs. ProtoGen+ accommodates a wide range of protocols, including those with hierarchy and heterogeneity. ProtoGen+ also generates the virtual network assignments necessary to avoid protocol deadlock. Two secondary objectives of the work are to explore the space of protocols that are compatible with ProtoGen+ and to produce protocols that are compatible with the previously developed Neo framework for verifiable protocol design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.