EAGER: Reconfigurable Network Hardware for Message-Driven Systems

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Message passing has long been known as a powerful tool for structuring parallel and distributed computation. Systems dating back more than 30 years have been built around message passing as the fundamental interprocess communications primitive. However, the use of message passing has been restricted to relatively coarse-grained application architectures due to message passing overhead. This project provides hardware to support an initial demonstration of coupling programmable network interfaces (10 Gbps NetFPGAs) into process scheduling in support of fine-grained message passing.The project explores novel hardware and software support for message-driven computation based on the concept of futures, a nearly 40 year old concept from programming languages. It also builds on both the NetFPGA platform and the memory models made available by the PCI-E bus and processors such as the latest Intel Xeon E5 series processors. Using the hardware support for locks and transactional memory as well as Data-Direct I/O into the cache in combination with a process execution model based on futures, this new approach to futures and message-driven scheduling revisits powerful historical approaches like dataflow in a realistic framework that stands to have impact in high-performance parallel computing and scalable network service architectures.