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Collaborative Research: nm Electron Wave Devices for Low-Power VLSI Electronics

Collaborative Research: nm Electron Wave Devices for Low-Power VLSI Electronics
合作研究:用于低功耗超大规模集成电路电子器件的纳米电子波器件
批准号:
1509288
负责人:
Mark Rodwell
金额:
$18.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-09-15 至 2018-08-31

项目摘要

项目成果

Mark Rodwell的其他基金

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相关文献

中文摘要
翻译
晶体管是现代集成电路(IC)的关键元件。由于一个典型的电路有数十亿个晶体管,在晶体管操作过程中产生的热量限制了芯片运行的速度和它可以包含的晶体管数量。工业界正在寻求一种电源电压尽可能低、漏电流最小的晶体管设计。为了快速切换,它必须在通电时提供大电流。关断电流与导通电流的比率由一个称为亚阈值摆动(SS)的系数决定;在正常的晶体管中,SS被限制为每十年0.06伏,即开关比中每10:1的系数需要0.06伏的电源电压,而典型的10到8的开关比需要8*0.06V,或大约0.5伏。已经提出了隧道晶体管来降低SS,但这些晶体管的导通电流很小,因为电子隧穿的概率非常小,因此对电流有贡献。没有穿过晶体管的电子会被反射。利用电子的波动性质,我们将通过使用额外的反射器来抑制反射,这种结构非常类似于抑制来自相机镜头表面的光的反射的涂层。如果电子没有被反射,它就会通过晶体管,导通电流增加。我们还将开发另一种低SS晶体管,超晶格晶体管,它利用电子波特性在晶体管关闭时阻止传输,而不是在打开时阻止传输。该项目的成功将使IC功耗降低约5:1,从而使计算机获得更快、更大、更有用的芯片。这是一个关键的更广泛的影响。一个智力上更广泛的影响是在一个广泛的公共应用设备中使用基础物理,即电子量子干涉。REU和暑期实习是另一个更广泛的影响。该项目旨在用一种新的器件取代VLSI中的现代晶体管,该器件工作在较低的电压下,用于低开关功率,但提供低关态电流,用于低待机功率,高导通电流,用于高速。一种提出的晶体管是隧道FET,它具有低工作电压但低导通电流,并增加了对反射的电子波产生破坏性干涉的电子波反射器。这抑制了电子反射,从而增加了透射率,从而开启了电流。第二个晶体管使用电子源中的超晶格来抑制超热电子,从而产生比玻尔兹曼分布更尖锐的开:关特性。这允许在低电压下实现较大的通断比。我们将对这些晶体管进行建模(模拟)设计、制造和测试。建模将使用量子传输模拟器(NEMO),并增加散射。制造需要标准的FET制造工艺(在UCSB很好地建立),但增加了在MBE沟道生长或在晶体管的MOCVD重新生长期间形成的电子能量过滤器。其智力意义是显而易见的:相干电子效应是大众市场电子设备的基础。
英文摘要
Transistors are the key element in modern integrated circuits (ICs). Since a typical circuit has billions of transistors, heat generated during transistor operation limits how fast the chip can operate and how many transistors it can contain. Industry is seeking a transistor design with the lowest possible power-supply voltage and the smallest amount of leakage current when it is off. To switch quickly, it must provide large currents when it is on. The ratio of off-current to on current is determined by a factor called the sub-threshold swing (SS); in a normal transistor the SS is limited to 0.06 Volts per decade, i.e. each factor of 10:1 in the on-off ratio requires 0.06 Volts power supply voltage, and a typical 10 to the eighth on/off ratio requires 8*0.06V, or about 0.5 Volts. Tunnel transistors have been proposed to reduce the SS, but these have small on-currents because the probability of an electron tunneling, hence contributing to current, is very small. An electron which does not tunnel through the transistor is instead reflected. Exploiting the wave nature of electrons, we will suppress the reflection by using additional reflectors, in a structure much like the coatings which suppress the reflection from light from the surface of a camera lens. If the electron is not reflected, it instead passes through the transistor, and the on-current is increased. We will also develop another low-SS transistor, a superlattice transistor, which exploits electron wave properties to block transmission when the transistor is off but not when it is on. Success in the project would allow a ~5:1 reduction in IC power consumption, leading to faster, bigger, and more useful chips benefitting computers. This is a key broader impact. An intellectual broader impact is the use of fundamental physics, electron quantum interference in a device of vast public application. REU and summer internships are another broader impact. The project seeks to replace the modern transistor in VLSI, a vast industry, with a new device, operating at lower voltage, for low switching power, yet giving low off-state current, for low standby power, and high on current, for high speed. One proposed transistor is a tunnel-FET, which has low operating voltage but low on-current, with added electron wave reflectors which cause destructive interference of the reflected electron wave. This suppresses electron reflection, hence increases transmission, hence on-current. The second transistor uses a superlattice in the electron source to suppress hot electrons, thereby producing on:off characteristics sharper than a Boltzmann distribution. This allows large on:off ration at low voltages. We will model (simulate) design, build and test these transistors. Modelling will use quantum transport simulators (NEMO) with the addition of scattering. Fabrication requires standard FET fabrication processes (well established at UCSB), but adds electron energy filters formed either during MBE channel growth or during MOCVD regrowth of the transistors. The intellectual significance is clear: coherent electron effects as the basis of a mass-market electron device.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
E2CDA: Type I: Collaborative Research: A Fast 70mV Transistor Technology for Ultra-Low-Energy Computing
NEB: Superlattice-FETs, Gamma-L-FETs, and Tunnel-FETs: Materials, Devices and Circuits for Fast Ultra-Lower-Power ICs
Presidential Young Investigators Award: Picosecond Electronic Circuits
国内基金
海外基金
Research on Quantum Field Theory without a Lagrangian Description
  • 批准号:
    24ZR1403900
  • 项目类别:
    省市级项目
  • 资助金额:
    --
  • 批准年份:
    2024
  • 负责人:
    SATOSHI NAWATA
  • 依托单位:
Cell Research
Cell Research
Cell Research (细胞研究)