NEB: Superlattice-FETs, Gamma-L-FETs, and Tunnel-FETs: Materials, Devices and Circuits for Fast Ultra-Lower-Power ICs
NEB:超晶格 FET、Gamma-L-FET 和隧道 FET:用于快速超低功耗 IC 的材料、器件和电路
基本信息
- 批准号:1125017
- 负责人:
- 金额:$ 128万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2011
- 资助国家:美国
- 起止时间:2011-09-01 至 2016-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Intellectual merit: This project is awarded under the Nanoelectronics for 2020 and Beyond competition, with support by multiple Directorates and Divisions at the National Science Foundation as well as by the Nanoelectronics Research Initiative of the Semiconductor Research Corporation. Progress in transistor and integrated circuit (IC) scaling has slowed, in part because of physical limits of transistor operation at small dimensions, but primarily because power consumption and power density are becoming excessive as complexity and density are further increased. IC power density results from opposing constraints in transistor and circuit design; the electron thermal distribution sets a minimum transistor control voltage for low off-state dissipation, while the dissipated energy on interconnects increases as the square of voltage. Addressing these limitations, radical changes in transistor design are proposed. To increase the on-current, designs are proposed that will overcome the so-called density of states (DOS) bottleneck in III-V semiconductors, adding additional valleys to those used in transport, therefore increasing the amount of charge that can be transported through the device at a high velocity. To increase drive current in N-channel field effect transistors (FETs) and the IC speed at reduced voltages III-V transistors will be develop using for the first time transport in the L (satellite) valleys, i.e. L-valley electronics. These will use the light electron part of their dispersion in the transport direction for fast carriers and will use the heavy electron characteristics to pack multiple bands into the ?same? energy space. Similar density of states engineering will be applied to P-channel FETs, achieved using light- and heavy-hole states mixed by strain and quantum confinement. To reduce supply voltages, steep transistors will be developed, having I-V characteristics varying much more rapidly than a thermal distribution. In addition to established tunnel injection devices having only moderate on-current, high-current steep-FETs will be developed. These use transport in energy bands of tightly constrained energy range, produced using 1-D semiconductor superlattices. Combining these two classes transisto rs, state-density-engineered transistors designed for high drive currents at low voltage, and steep transistors designed for very low off-state leakage, the program will explore new logic gate designs providing low power and high speed.Broader Impacts: The proposed work seeks to increase the speed and complexity, and reduce the power consumption of ICs. The industry is of enormous worldwide value. The participants interact regularly with the VLSI industry, communicating ongoing work and seeking guidance, and will continue with this model in the NSF program. Development of high-speed yet low-power logic devices will circumvent present power-consumption limits now constraining VLSI speed and complexity. This program will enable further large increases in the speed and power-limited computational performance of ICs, benefiting applications in industry, commerce, and personal use. Ph.D. students will be trained in semiconductor materials, device physics, and IC design. Their training will emphasize the interaction of system and circuit design with device design. Simulation tools will be developed and distributed by nanoHub to a worldwide user community. The program will operate a summer internship program, affiliated with that of the NNIN, providing laboratory experience exposure to a research environment for 8 undergraduate students.
智力优势:该项目是根据2020年及以后的纳米电子学竞赛授予的,得到了国家科学基金会多个董事和部门的支持,以及半导体研究公司的纳米电子研究计划的支持。晶体管和集成电路(IC)规模化方面的进展已经放缓,部分原因是晶体管在小尺寸操作的物理限制,但主要是因为随着复杂性和密度的进一步增加,功耗和功率密度变得过大。集成电路的功率密度是由晶体管和电路设计中的相反约束决定的;电子热分布为低关态功耗设定了最小晶体管控制电压,而互连线上的耗散能量随着电压的平方而增加。针对这些局限性,提出了晶体管设计的根本改变。为了增加导通电流,提出了克服III-V半导体中所谓的态密度(DOS)瓶颈的设计,在传输中使用的态密度(DOS)增加了额外的谷,从而增加了可以通过该器件高速传输的电荷量。为了提高N沟道场效应晶体管(FET)的驱动电流和降低电压下的集成电路速度,将首次利用L(卫星)谷的运输,即L谷电子,开发III-V晶体管。它们将利用其在快速载流子传输方向上的色散中的轻电子部分,并利用重电子特性将多个带包装成相同的?能量空间。类似的态密度工程将应用于P沟道FET,使用应变和量子限制混合的轻空穴态和重空穴态实现。为了降低电源电压,将开发陡峭的晶体管,其I-V特性的变化比热分布快得多。除了现有的只有中等导通电流的隧道注入器件外,还将开发大电流陡峭FET。它们使用一维半导体超晶格在能量范围受到严格限制的能带中进行传输。结合这两类晶体管,为低电压下的高驱动电流设计的状态密度工程晶体管和为极低关态泄漏而设计的陡峭晶体管,该计划将探索提供低功耗和高速度的新的逻辑门设计。广泛的影响:拟议的工作旨在提高IC的速度和复杂性,并降低功耗。该行业在全球范围内具有巨大的价值。参与者定期与VLSI行业互动,交流正在进行的工作并寻求指导,并将在NSF计划中继续使用这一模式。高速但低功耗逻辑器件的开发将绕过目前制约VLSI速度和复杂性的现有功耗限制。该计划将使IC的速度和功率有限的计算性能进一步大幅提高,使工业、商业和个人使用中的应用受益。博士生将接受半导体材料、器件物理和集成电路设计方面的培训。他们的培训将强调系统和电路设计与器件设计的互动。模拟工具将由NanHub开发并分发给世界各地的用户社区。该计划将实施一个附属于NNIN的暑期实习计划,为8名本科生提供接触研究环境的实验室经验。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
数据更新时间:{{ journalArticles.updateTime }}
{{
item.title }}
{{ item.translation_title }}
- DOI:
{{ item.doi }} - 发表时间:
{{ item.publish_year }} - 期刊:
- 影响因子:{{ item.factor }}
- 作者:
{{ item.authors }} - 通讯作者:
{{ item.author }}
数据更新时间:{{ journalArticles.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ monograph.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ sciAawards.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ conferencePapers.updateTime }}
{{ item.title }}
- 作者:
{{ item.author }}
数据更新时间:{{ patent.updateTime }}
Mark Rodwell其他文献
Mark Rodwell的其他文献
{{
item.title }}
{{ item.translation_title }}
- DOI:
{{ item.doi }} - 发表时间:
{{ item.publish_year }} - 期刊:
- 影响因子:{{ item.factor }}
- 作者:
{{ item.authors }} - 通讯作者:
{{ item.author }}
{{ truncateString('Mark Rodwell', 18)}}的其他基金
E2CDA: Type I: Collaborative Research: A Fast 70mV Transistor Technology for Ultra-Low-Energy Computing
E2CDA:类型 I:协作研究:用于超低能耗计算的快速 70mV 晶体管技术
- 批准号:
1640030 - 财政年份:2016
- 资助金额:
$ 128万 - 项目类别:
Continuing Grant
Collaborative Research: nm Electron Wave Devices for Low-Power VLSI Electronics
合作研究:用于低功耗超大规模集成电路电子器件的纳米电子波器件
- 批准号:
1509288 - 财政年份:2015
- 资助金额:
$ 128万 - 项目类别:
Standard Grant
Presidential Young Investigators Award: Picosecond Electronic Circuits
总统青年研究员奖:皮秒电子电路
- 批准号:
8958327 - 财政年份:1989
- 资助金额:
$ 128万 - 项目类别:
Continuing Grant
相似海外基金
CO2-coupled photothermal catalysis on superlattice structures
超晶格结构上的 CO2 耦合光热催化
- 批准号:
DP240102707 - 财政年份:2024
- 资助金额:
$ 128万 - 项目类别:
Discovery Projects
Resonant tunneling diode Terahertz oscillator with superlattice heterostructure for high output power
具有超晶格异质结构的谐振隧道二极管太赫兹振荡器,可实现高输出功率
- 批准号:
24K17329 - 财政年份:2024
- 资助金额:
$ 128万 - 项目类别:
Grant-in-Aid for Early-Career Scientists
Potassium Atoms in 2D Triangular Superlattice
二维三角形超晶格中的钾原子
- 批准号:
2309300 - 财政年份:2023
- 资助金额:
$ 128万 - 项目类别:
Continuing Grant
Investigation of Carrier Transport Process in Undulated Superlattice and Development of High Carrier Density Solar Cells for Hydrogen Production
起伏超晶格中载流子输运过程的研究及高载流子密度制氢太阳能电池的开发
- 批准号:
22KJ0955 - 财政年份:2023
- 资助金额:
$ 128万 - 项目类别:
Grant-in-Aid for JSPS Fellows
EAGER: Superlattice-induced polycrystalline and single-crystalline structures in conjugated polymers
EAGER:共轭聚合物中超晶格诱导的多晶和单晶结构
- 批准号:
2203318 - 财政年份:2022
- 资助金额:
$ 128万 - 项目类别:
Standard Grant
ECCS-EPSRC Superlattice Architectures for Efficient and Stable Perovskite LEDs
用于高效稳定钙钛矿 LED 的 ECCS-EPSRC 超晶格架构
- 批准号:
EP/V06164X/1 - 财政年份:2022
- 资助金额:
$ 128万 - 项目类别:
Research Grant
Self-assembly of modified nanocomposite tectons (NCTs) into superlattice structures for self-healing materials
将改性纳米复合材料(NCT)自组装成超晶格结构,用于自修复材料
- 批准号:
567947-2022 - 财政年份:2022
- 资助金额:
$ 128万 - 项目类别:
Postgraduate Scholarships - Doctoral
Realization of integrated high sensitivity electric field sensor using quantum dot superlattice
利用量子点超晶格实现集成高灵敏度电场传感器
- 批准号:
22K04218 - 财政年份:2022
- 资助金额:
$ 128万 - 项目类别:
Grant-in-Aid for Scientific Research (C)
Development of ferroelectric superlattice thin films for next-generation energy storage devices
开发用于下一代储能器件的铁电超晶格薄膜
- 批准号:
22K14479 - 财政年份:2022
- 资助金额:
$ 128万 - 项目类别:
Grant-in-Aid for Early-Career Scientists
ECCS-EPSRC Superlattice Architectures for Efficient and Stable Perovskite LEDs
用于高效稳定钙钛矿 LED 的 ECCS-EPSRC 超晶格架构
- 批准号:
EP/V061747/1 - 财政年份:2021
- 资助金额:
$ 128万 - 项目类别:
Research Grant