FOundations of Secure and TrustEd HardwaRe (FOSTER) Workshop

安全和可信硬件基础 (FOSTER) 研讨会

• 批准号: 1749175
• 负责人: Siddharth Garg
• 金额: $ 4.5万
• 依托单位: New York University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2018-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1749175&HistoricalAwards=false
• 关键词: FOundations; Secure; TrustEd; HardwaRe; FOSTER

Semiconductor microchips are the brains inside all of the electronic devices that pervade our society. To control costs, microchips are often designed and even manufactured off-shore. Outsourcing the design and fabrication of semiconductor microchips comes at the expense of their security. For one, an off-shore microchip foundry can copy or steal the chip's blueprint, and sell copies of the chip in the black market. Perhaps worse, the foundry can also modify the chip's blueprint in stealthy ways, such that modifications go undetected and the chip misbehaves in harmful ways. The vulnerabilities affect the bottom-lines of commercial U.S. chip design companies, but perhaps more critically, threaten the integrity of electronic components used in defense equipment and critical infrastructure. There has been more than a decade of fruitful academic and industry research on solutions to counteract these threats to the design, manufacturing, and supply of electronic components. However, there is still no common consensus on questions of critical importance. For instance, what are the most pernicious attack vectors, in the near and far term? And, how can we quantitatively compare different defense mechanisms in terms of the security they offer? The time is ripe to bring together experts from government, industry and academia to lay the foundations for the next phase of hardware security research and reach a broad consensus on the most critical challenges, identify promising defense mechanisms and establish methodologies to evaluate solutions. The FOSTER Workshop is aimed at meeting this challenge. The format of the workshop will encourage deep and open discussion between key stakeholders, and its outcome will be a comprehensive report that lays out a roadmap for research and transitioning research outcomes to practice.Globalization of the IC design flow has reduced design complexity and fabrication cost, but has introduced several security vulnerabilities. A rogue agent anywhere in the IC supply chain can perform the following attacks: reverse engineering, hardware Trojans insertion, counterfeiting (specifically, recycled ICs), and IP piracy. These attacks cost the semiconductor industry billions of dollars annually, undermine national security and put critical infrastructure in danger. Despite the severity of this problem, current commercial IC design tools, for the most part, do not consider security as a first-class design metric. More than a decade of hardware security research has been instrumental in identifying and analyzing the key problems in this area and proposing a diverse array of solutions that address different attack surfaces. As hardware security research moves to a new phase of maturity, there is an urgent need to synthesize multiple threads of research into a synergistic security-aware EDA tool-flow that will enable the next generation of trusted hardware platforms.The FOSTER Workshop aims to address this need. The workshop will bring together leading experts from industry and academia to address the following foundational topics: (1) characterizing the hardware security attack surface; (2) identifying formal, quantitative metrics to evaluate and benchmark security solutions; (3) identifying the most promising defense mechanisms and understand how different solutions can work synergistically. The outcomes of the workshop will be of interest to EDA tool developers, fabless semiconductor design companies, silicon foundries, test companies, embedded system companies, computer and communication security companies, and US government agencies, and will eventually benefit trustworthy electronics for healthcare, defense, finance, transportation, and automotive applications.

半导体微芯片是弥漫在我们社会中的所有电子设备的大脑。为了控制成本，微芯片通常是在海外设计甚至制造的。将半导体微芯片的设计和制造外包是以牺牲其安全性为代价的。首先，离岸微芯片代工厂可以复制或窃取芯片的蓝图，然后在黑市上出售芯片的复制品。也许更糟糕的是，代工厂还可以以秘密的方式修改芯片的蓝图，这样修改就不会被发现，芯片就会以有害的方式行为不当。这些漏洞影响到美国商业芯片设计公司的底线，但或许更严重的是，它们威胁到了用于国防设备和关键基础设施的电子元件的完整性。十多年来，学术界和业界对解决方案进行了卓有成效的研究，以对抗这些对电子零部件设计、制造和供应的威胁。然而，在至关重要的问题上仍然没有达成共同的共识。例如，在近期和远期内，最有害的攻击媒介是什么？而且，我们如何才能量化地比较不同的防御机制提供的安全性？召集政府、行业和学术界的专家为下一阶段的硬件安全研究奠定基础，并就最关键的挑战达成广泛共识，确定有前景的防御机制，并建立评估解决方案的方法，时机已经成熟。福斯特研讨会旨在迎接这一挑战。研讨会的形式将鼓励关键利益相关者之间进行深入和开放的讨论，其结果将是一份全面的报告，其中列出了研究和将研究成果转化为实践的路线图。IC设计流程的全球化降低了设计复杂性和制造成本，但也引入了几个安全漏洞。IC供应链中任何地方的流氓代理都可以执行以下攻击：反向工程、硬件特洛伊木马插入、假冒(特别是回收IC)和IP盗版。这些攻击每年给半导体行业造成数十亿美元的损失，破坏国家安全，并将关键基础设施置于危险之中。尽管这个问题很严重，但目前的商业IC设计工具在很大程度上并没有将安全性作为一流的设计指标。十多年的硬件安全研究有助于识别和分析该领域的关键问题，并提出一系列解决方案，以应对不同的攻击面。随着硬件安全研究进入一个新的成熟阶段，迫切需要将多个研究线程综合到一个协同的安全感知EDA工具流中，以支持下一代可信硬件平台。福斯特研讨会旨在满足这一需求。研讨会将汇集业界和学术界的顶尖专家，讨论以下基本主题：(1)确定硬件安全攻击面的特征；(2)确定正式的量化指标，以评估和基准安全解决方案；(3)确定最有希望的防御机制，并了解不同的解决方案如何协同工作。研讨会的成果将使EDA工具开发商、无工厂半导体设计公司、硅铸造厂、测试公司、嵌入式系统公司、计算机和通信安全公司以及美国政府机构感兴趣，并最终将使医疗保健、国防、金融、交通和汽车应用领域的值得信赖的电子产品受益。