SHF: Medium: PRISM: Platform for Rapid Investigation of efficient Scientific-computing & Machine-learning

今天的系统需要使用大量数据集加速处理和学习。不幸的是，由于较差的能量扩展和功率限制，通用处理器中由于技术扩展和指令级并行性而带来的性能和功率改进已经结束。众所周知，完全定制的、特定于应用程序的硬件加速器可以为各种应用程序领域提供数量级的能量/op改进。因此，人们对能够优化和加速机器学习和数据科学例程构建块的系统特别感兴趣。许多这些构建块与处理矩阵的高性能计算内核的构建块具有相同的特征。这种针对特定应用的解决方案依赖于算法和硬件的联合优化，但成本高达数亿美元。PRISM（高效科学计算和机器学习加速器快速研究平台）的提出是为了摊销这些成本。PRISM使应用程序设计人员能够快速获得关于其算法的可用并行性和局部性的反馈，以及由此产生的应用程序/硬件设计的效率。PRISM平台由两个耦合的工具组成，这些工具包含硬件和算法级别的设计知识。这种知识使应用程序设计人员能够快速评估其应用程序在拟议/现有硬件上的性能，而应用程序设计人员不需要成为硬件或算法方面的专家。该平台将利用团队先前研究创建的工具。最初，将使用这些工具为每个应用程序创建一个有效的解决方案，然后比较得到的硬件设计。然后可以探索创建跨越多个算法类别的平台的可能性。最后，将这些新架构与现有的具有gpu和fpga的异构架构进行比较，以了解在支持这些类算法时，这些架构需要进行哪些修改才能达到更高的效率水平。对关键应用程序的研究将使我们更好地了解这些计算所固有的计算和通信，并为这些应用程序提供在传统和新架构上有效的算法。

Today's systems demand acceleration in processing and learning using massive datasets. Unfortunately, because of poor energy scaling and power limits, performance and power improvements due to technology scaling and instruction level parallelism in general-purpose processors have ended. It is well known that full custom, application-specific hardware accelerators can provide orders-of-magnitude improvements in energy/op for a variety of application domains. Therefore, there is a special interest in systems that can optimize and accelerate the building blocks of machine learning and data science routines. Many of these building blocks share the same characteristics as building blocks of high performance computing kernels working on matrices. Such application specific solutions rely on joint optimization of algorithms and the hardware, but cost hundreds of millions of dollars. PRISM (Platform for Rapid Investigation of efficient Scientific- computing and Machine-learning accelerators) is proposed to amortize these costs. PRISM enables application designers to get rapid feedback about both the available parallelism and locality of their algorithm, and the efficiency of the resulting application/hardware design. PRISM platform consists of two coupled tools that incorporate design knowledge at both the hardware and algorithm level. This knowledge enables the tool to give application designers the ability to quickly evaluate the performance of their applications on the proposed/existing hardware, without the application designer needing to be an expert at hardware or algorithms. This platform will leverage tools created from the team's prior research. Initially, these tools will be used to create an efficient solution for each application, followed by a comparison of the resulting hardware designs. The possibility of creating platforms that span multiple classes of algorithms can then be explored. Finally, a comparison of these new architectures to existing heterogeneous architectures with GPUs and FPGAs will be made, to gain understanding about what modifications are necessary for these architectures to achieve higher levels of efficiency when supporting these classes of algorithms. The work on key applications will lead to better insight about the computation and communication intrinsic to these computations, and provide algorithms for these applications that will be effective on conventional and new architectures.