SHF: Small: Exploiting the Negative Capacitance in a new Ferroelectric Device to Explore Innovative Design Solutions beyond the Fundamental Thermionic Limit of CMOS Technology

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Over the last sixty years silicon based integrated circuit technologies have been successfully meeting the demands of higher performance and lower energy consumption through the miniaturization of the transistor and circuit dimensions. As the conventional devices and materials are now approaching their fundamental physical limits, new devices and circuits and materials need to be investigated for the next generation logic, memory, sensor and energy harvesting applications. Within this framework, the proposed research on a new nanoscale ultra-low-power electronic device makes use of convergence of technologies in advanced computing, electronic engineering, mathematics, physics, chemistry and information-theory. This EPSCoR initiative would directly or indirectly impact a large number of students of the PI's institution, and an even larger number of local high school and pre-collegiate students through the Kansas City STEM Alliance, for which the PI plans to develop a summer bridge program to promote nanotechnology education. From a technical standpoint the project plans to develop a new field effect transistor (FET) technology to achieve an effective negative capacitance (NC) inside the transistor structure by utilizing ferroelectric materials. It has recently been reported that ferroelectric materials can provide a negative capacitance that can be the solutions to many of the challenges of nanoelectronics. While many contemporary researchers are investigating ways to exploit this NC effect to break the performance and energy efficiency barriers of the existing silicon based transistors, the proposed effort combines the concept of the emerging negative capacitance based field effect transistor (NCFET) and the conventional silicon-on-insulator (SOI) technologies.