SHF: Small: SlackTrack: Efficiently Exploiting Circuit Slack in Multi-Cycle Datapaths

SHF：小型：SlackTrack：有效利用多周期数据路径中的电路空闲

• 批准号: 1615014
• 负责人: Mikko Lipasti
• 金额: $ 44.99万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-06-15 至 2020-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1615014&HistoricalAwards=false
• 关键词: SHF; Small; SlackTrack; Efficiently; Exploiting

The microprocessor and system-on-chip industry is increasingly focused on mobile platforms, where maximizing battery life is paramount. As a result, static and dynamic power consumption are now primary design constraints for general-purpose microprocessors. In response, chip designers are integrating a plethora of customized on-die accelerators, which reduce energy consumption because their control logic, datapaths, interconnect, and memory are tailored for a specific task. This project tackles the main remaining source of power consumption in accelerators clocked storage elements and investigates the design of novel accelerators with very few such elements. Without these kinds of dramatic innovations in the design of power-efficient, high-performance chips, the continued device scaling of future nanometer technologies may no longer provide substantial returns in utility or performance. As a result, the microprocessor industry, and by extension, the computer industry as a whole, faces a serious challenge in maintaining the growth-based business model that has sustained it for four decades. This research has broad industry- and economy-wide impact since it helps to address or avert these challenges. The findings from this project will be integrated into graduate level courses which will help students get a more in depth understanding of the power wall issue which is a big challenge for architects in the near future.Removing the overheads imposed by clocked elements will enable accelerator designs to approach a true energy lower bound for the cost of computation. Furthermore, pipeline latch removal also exposes additional opportunities for improvement to the power efficiency and performance of datapath circuits. Most importantly, since the critical delay paths in a multi-cycle datapath span multiple clock cycles and traverse many more levels of logic than the base naive pipeline, the likelihood that random and within-die variations will slow down a critical path is substantially lower. In other words, since critical paths are two, four, or even more times longer than in the base case, random and within-die process variations are amortized over a longer total delay path and are more likely to cancel each others' effects, leading to a smaller net effect on achievable cycle time. This tightened variance can be exploited to reduce design-time margins, allowing the datapath to be operated at a lower voltage for a given frequency. Furthermore, novel run-time approaches for measuring and controlling available slack in the circuit's operation enable aggressive timing speculation, allowing the datapath to run at nearly nominal frequencies while minimizing operating voltage.

微处理器和片上系统行业越来越关注移动的平台，其中最大限度地延长电池寿命至关重要。因此，静态和动态功耗现在是通用微处理器的主要设计约束。作为回应，芯片设计师正在集成大量定制的片上加速器，这可以降低能耗，因为它们的控制逻辑、数据路径、互连和存储器是针对特定任务量身定制的。这个项目解决了加速器时钟存储元件中的主要剩余功耗源，并研究了具有很少此类元件的新型加速器的设计。如果在设计高能效、高性能芯片方面没有这些引人注目的创新，未来纳米技术的持续器件扩展可能不再提供实用性或性能方面的实质性回报。因此，微处理器行业，乃至整个计算机行业，在维持40年来以增长为基础的商业模式方面面临着严峻的挑战。这项研究具有广泛的行业和经济范围的影响，因为它有助于解决或避免这些挑战。该项目的研究结果将被整合到研究生课程中，这将帮助学生更深入地了解电力墙问题，这是建筑师在不久的将来面临的一个巨大挑战。消除时钟元件带来的开销将使加速器设计接近计算成本的真正能量下限。此外，管线锁存器移除还暴露了用于改进数据路径电路的功率效率和性能的额外机会。最重要的是，由于多周期数据路径中的关键延迟路径跨越多个时钟周期并且比基本朴素流水线遍历更多的逻辑级，因此随机和管芯内变化将使关键路径变慢的可能性显著降低。换句话说，由于关键路径比基本情况长两倍、四倍或甚至更多倍，因此随机和管芯内工艺变化在更长的总延迟路径上被分摊，并且更可能抵消彼此的影响，从而导致对可实现的周期时间的更小的净影响。可以利用这种收紧的变化来减少设计时裕度，从而允许数据路径在给定频率下以较低电压操作。此外，用于测量和控制电路操作中的可用松弛的新颖运行时间方法实现了积极的时序推测，允许数据路径以接近标称频率运行，同时最小化操作电压。