STARSS: Small: SecureDust -- The Physical Limits of Information Security

用非常小的、自供电和无线联网的集成电路进行真正的无处不在的计算将在十年内成为可能。这些设备的应用包括生物传感器、环境监测器和国防，所有这些都带来了安全和隐私的需求。要在极其受限的设备上使用强大的加密算法，需要从能源优先的角度重新考虑基本加密构建块的设计和实现。安全尘埃项目寻求将先进技术中的加密功能的能量降低一个数量级，并使用测试芯片验证设计。该项目的研究结果将有助于确保未来无处不在的设备和物联网的安全。该项目的具体研究目标是探索将安全功能缩减到先进的CMOS技术中，特别是制造变异和噪声的重要作用，这些变化和噪声可能是有利的(物理不可克隆函数和随机数生成)，也可能是有害的(抗侧信道密码和散列函数)，具体取决于密码块。我们的目标是每笔安全交易的能源预算为皮焦耳，建立在基本的加密功能基础上。该项目结合了使用分组密码、散列函数、PUF和RNG的轻量级密码学方面的设计专业知识，以及低能耗技术和现实的半导体设计流程和经济现实。将使用现场可编程门阵列原型和CMOSFinFET测试芯片来演示完整的密码系统功能，包括旁路敏感性。

Truly ubiquitous computing with very small, self-powered and wirelessly networked integrated circuits will become possible within a decade. Applications of these devices include biosensors, environmental monitors, and defense, all of which bring a need for security and privacy. Enabling the use of strong cryptographic algorithms on extremely constrained devices requires rethinking, from an energy-first perspective, the design and implementation of basic cryptographic building blocks. The Secure Dust project seeks to reduce the energy of cryptographic functions in advanced technologies by an order of magnitude, and to validate the designs using test chips. The findings of this project will help to secure future ubiquitous devices and the Internet of Things.The specific research objective of this project is to explore the scaling down of security functions into advanced CMOS technologies and in particular the important role of manufacturing variations and noise that can be both advantageous (Physical Unclonable Functions and Random Number Generation) and detrimental (side-channel resistant ciphers and hash functions) depending on the cryptography block. We target an energy budget of picojoules per secure transaction, built upon basic cryptography functions. The project combines design expertise in lightweight cryptography using block ciphers, hash functions, PUFs and RNGs, along with low-energy techniques and realistic semiconductor design flows and economic realities. FPGA-prototyping and CMOS FinFET test chips will be used to demonstrate complete cryptosystem functionality, including side-channel susceptibility.