XPS: FULL: Breaking the Scalability Wall of Shared Memory through Fast On-Chip Wireless Communication

随着晶体管尺寸的不断扩大，我们即将见证惊人的芯片集成水平，单个芯片上有1000个内核。在这些处理器数量上，许多研究人员都认为共享内存无法扩展。原因是支持这么多内核之间的细粒度同步和通信需要很高的硬件开销。这项研究试图反驳这一点。它表明，通过使用快速片上无线通信，细粒度数据共享是可扩展的。主要研究人员（pi）用收发器增强每个核心，使片上广播在5-7纳秒内实现，并设计了一个支持它的多核架构。然后，pi实现同步和通信原语和库，以前所未有的低开销支持细粒度数据共享。有了这些原语，pi重新设计了流行的运行时，如OpenMP或Cilk，并重新考虑了算法和应用程序。这项工作有助于伊利诺伊大学在可扩展并行计算方面的多学科研究和教育。pi将加强他们所教授的并行计算机体系结构、并行编译技术和并行编程方面的课程。他们还与该部门合作，扩大并行计算一般领域的多学科本科课程的课程设置——作为伊利诺伊州CS+X专业结构的一部分，其中X可以是大量其他学科。这项工作还将对工业产生影响，因为它解决了一个现实的、非常及时的技术问题：非凡的片上集成与不可扩展的细粒度数据共享。与IBM研究院和微软研究院紧密合作的能力将至关重要。这是一个跨学科的工作，横跨三个领域：体系结构、编程系统、算法和应用程序。该体系结构的工作重点是通过扩展缓存一致性事务、以错误率为代价的无线功率以及支持多个无线信道来支持片上无线通信。编程系统的工作重点是重新设计MPI通信原语，使共享内存可用于OpenMP和Cilk，并为应用程序弹性设计最佳API。算法和应用程序工作的重点是研究和开发可以利用该体系结构的算法和应用程序。pi研究图、数值、动态规划、识别-挖掘-合成和MapReduce等领域的问题。

As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die. At these processor counts, it has been an accepted tenet among many researchers that shared memory does not scale. The reason is the high hardware overhead of supporting fine-grain synchronization and communication between so many cores. This research seeks to disprove this. It shows that fine-grain data sharing is scalable with the use of fast on-chip wireless communication. The Principal Investigators (PIs) augment each core with a transceiver that enables on-chip broadcast in 5-7 nanoseconds, and design a multicore architecture that supports it. Then, the PIs implement synchronization and communication primitives and libraries that support fine-grain data sharing with an unprecendented low overhead. With these primitives, the PIs redesign popular runtimes such as OpenMP or Cilk, and rethink algorithms and applications. This effort contributes to multidisciplinary research and education on scalable parallel computing at the University of Illinois. The PIs will enhance the courses that they teach in parallel computer architecture, parallel compilation techniques, and parallel programming. They are also working with the department to broaden the course offerings with multidisciplinary undergraduate courses in the general area of parallel computing --- as part of Illinois' CS+X major structure, where X can be a large number of other disciplines. The work will also have an impact on industry, since it addresses a real, very timely technical problem: extraordinary on-chip integration coupled with unscalable fine-grain data sharing. The ability to work closely with IBM Research and Microsoft Research will be crucial.This is a cross-disciplinary effort that cuts across three areas: architecture, programming systems, and algorithms and applications. The architecture work focuses on supporting on-chip wireless communication by extending cache coherence transactions, trading-off wireless power for error rate, and supporting multiple wireless channels. The programming systems work focuses on redesigning the MPI communication primitives, making shared memory scalable for OpenMP and Cilk, and designing a best-effort API for application resiliency. The algorithms and applications work focuses on studying and developing algorithms and applications  that can take advantage of the architecture. The PIs study problems in the areas of graphs, numerics, dynamic programming, recognition-mining-synthesis, and MapReduce.