Technologies for Ultra Energy-Efficient Multicores

随着半导体器件的不断缩小，很明显，我们即将见证令人惊叹的集成水平。随着我们采用亚10纳米技术，我们将能够在单个芯片上集成超过1,000个相当大的内核和大量内存。此外，芯片堆叠将成为常态。在这种环境下，构建可用架构的主要障碍是能源和/或电力消耗。为了确保架构的进展不会受到这些限制的阻碍，需要从头开始重新设计架构以提高能效。这项工作将有助于开发一套技术，使下一代超节能多核。这种多核应用于包括能源、交通、环境或公共卫生在内的各种领域，将为我们的国家带来重大的经济和环境效益。PI设想这一努力有助于伊利诺伊大学先进节能计算机架构的研究和教育。PI目前正在教授计算机体系结构课程;他将通过本提案中的研究加强课程。该项目还将对工业产生重大影响，因为它解决了一个真实的、非常及时的技术问题。该研究项目分析了三种变革性、高风险和高回报的超节能多核技术。它们是：（1）灵活的多核，通过电压可扩展性或通过CMOS和TFET的组合实现大范围的操作;（2）用于能量、性能和其他参数的控制理论硬件控制器;以及（3）3D堆叠多核中的高级热支持。此外，它在一个关键领域从事研究，使用的方法与当前的研究趋势截然不同。

As semiconductor devices continue to shrink, it is clear that we are about to witness stunning levels of integration. As we proceed through sub-10nm technology, we will be able to integrate over 1,000 sizable cores and substantial memory on a single die. Moreover, die stacking will be the norm. In this environment, the main obstacle to building usable architectures is and will be energy and/or power consumption. To ensure that architecture progress is not bottlenecked by these limitations, architectures need to be redesigned for energy efficiency from the ground up. This work will help develop a set of technologies that will enable the next generation of ultra energy-efficient multicores. Such multicores, applied to a variety of domains that include energy, transportation, environment, or public health, will deliver major economic and environmental benefits to our nation. The PI envisions this effort as contributing to the research and education on advanced energy-efficient computer architecture at the University of Illinois. The PI is currently teaching courses in computer architecture; he will enhance the courses with the research in this proposal. The project will also have a major impact on industry, since it addresses a real, very timely technical problem.This research project analyzes three transformative, high-risk and high-payoff technologies for ultra energy-efficient multicores. They are: (1) flexible multicores with cores that attain a large range of operation, either through voltage scalability or through combining CMOS and TFET; (2) control-theoretic hardware controllers for energy, performance, and other parameters; and (3) advanced thermal support in 3D-stacked multicores. Moreover, it engages in research in a crucial area using approaches that are radically different from the current research trends.