EAGER: An Analog Hardware System for Solving Boolean Satisfiability

EAGER:用于解决布尔可满足性的模拟硬件系统

基本信息

  • 批准号:
    1644368
  • 负责人:
  • 金额:
    $ 29.96万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2016
  • 资助国家:
    美国
  • 起止时间:
    2016-07-15 至 2023-06-30
  • 项目状态:
    已结题

项目摘要

This proposal explores the design of a low-power and high-performance analog hardware system capable of solving Boolean Satisfiability (SAT) problem which is at the heart of many decision, scheduling, error-correction and cyber security applications. Since SAT belongs to a well-known family of hard decision problems in computer science, an efficient solution would have a profound impact in all of computational sciences, engineering, and societal applications. The project builds on close collaborations among theoreticians and hardware designers to create opportunities to cross-pollinate research areas that traditionally have had little intersection in this context. The project will allow the PIs to incorporate new research discoveries into relevant coursework, and offer research opportunities for undergraduate and graduate students, including those from underrepresented groups. This proposed effort will study the potential of analog hardware based on some related deterministic Continuous Time Dynamical System (CTDS) in the form of coupled ordinary differential equations, which have been recently introduced for the study of the SAT problem. The CTDS performs gradient descent on an energy function, which itself changes in time, coupled to the performance of the dynamics through exponentially driven auxiliary variables. The project will study systematically the question of whether and by how much a CTDS based analog hardware SAT solver can outperform digital SAT solvers in terms of performance and energy efficiency. It will also advance the understanding of the impact of hardware induced noises on analog SAT solvers. In summary, the project attempts to provide insights into the relationship between the nonlinear dynamical system properties of the analog solver and the computational hardness of constraint satisfaction problems, and thus lay the foundation for analog hardware designs for CTDS solvers, as well as that for SAT solvers.
该方案探索了一种能够解决布尔可满足性(SAT)问题的低功耗和高性能模拟硬件系统的设计,该问题是许多决策、调度、纠错和网络安全应用的核心。由于SAT属于计算机科学中众所周知的一类困难决策问题,因此一个有效的解决方案将对所有计算科学、工程和社会应用产生深远的影响。该项目建立在理论家和硬件设计师之间密切合作的基础上,以创造机会对传统上在这一背景下几乎没有交叉的研究领域进行交叉授粉。该项目将允许私人投资机构将新的研究发现纳入相关课程,并为本科生和研究生提供研究机会,包括那些来自代表性不足群体的学生。这项拟议的工作将基于一些相关的确定性连续时间动态系统(CTDS)来研究模拟硬件的潜力,这些系统以耦合常微分方程组的形式出现,最近被引入用于研究SAT问题。CTDS对能量函数执行梯度下降,该能量函数本身随时间变化,并通过指数驱动的辅助变量与动力学性能相结合。该项目将系统地研究基于CTDS的模拟硬件SAT解算器在性能和能源效率方面是否以及在多大程度上能够超过数字SAT解算器。它还将促进对硬件诱导噪声对模拟SAT解算器的影响的理解。综上所述,该项目试图深入了解模拟求解器的非线性动力系统特性与约束满足问题的计算难度之间的关系,从而为CTDS求解器以及SAT求解器的模拟硬件设计奠定基础。

项目成果

期刊论文数量(6)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Efficient Analog Circuits for Boolean Satisfiability
Bounded Continuous-Time Satisfiability Solver
有界连续时间可满足性求解器
An Analog SAT Solver Based on a Deterministic Dynamical System
基于确定性动力系统的模拟 SAT 求解器
An Ising Hamiltonian solver based on coupled stochastic phase-transition nano-oscillators
  • DOI:
    10.1038/s41928-021-00616-7
  • 发表时间:
    2021-07-01
  • 期刊:
  • 影响因子:
    34.3
  • 作者:
    Dutta, S.;Khanna, A.;Datta, S.
  • 通讯作者:
    Datta, S.
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Siddharth Joshi其他文献

FDI, Poverty, and the Politics of Potable Water Access
外国直接投资、贫困和饮用水获取政治
DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity
DropOut 和 DropConnect 在网络连接的能量和带宽约束下实现可靠​​的神经形态推理
The neurobench framework for benchmarking neuromorphic computing algorithms and systems
用于神经形态计算算法和系统基准测试的神经基准框架
  • DOI:
    10.1038/s41467-025-56739-4
  • 发表时间:
    2025-02-11
  • 期刊:
  • 影响因子:
    15.700
  • 作者:
    Jason Yik;Korneel Van den Berghe;Douwe den Blanken;Younes Bouhadjar;Maxime Fabre;Paul Hueber;Weijie Ke;Mina A. Khoei;Denis Kleyko;Noah Pacik-Nelson;Alessandro Pierro;Philipp Stratmann;Pao-Sheng Vincent Sun;Guangzhi Tang;Shenqi Wang;Biyan Zhou;Soikat Hasan Ahmed;George Vathakkattil Joseph;Benedetto Leto;Aurora Micheli;Anurag Kumar Mishra;Gregor Lenz;Tao Sun;Zergham Ahmed;Mahmoud Akl;Brian Anderson;Andreas G. Andreou;Chiara Bartolozzi;Arindam Basu;Petrut Bogdan;Sander Bohte;Sonia Buckley;Gert Cauwenberghs;Elisabetta Chicca;Federico Corradi;Guido de Croon;Andreea Danielescu;Anurag Daram;Mike Davies;Yigit Demirag;Jason Eshraghian;Tobias Fischer;Jeremy Forest;Vittorio Fra;Steve Furber;P. Michael Furlong;William Gilpin;Aditya Gilra;Hector A. Gonzalez;Giacomo Indiveri;Siddharth Joshi;Vedant Karia;Lyes Khacef;James C. Knight;Laura Kriener;Rajkumar Kubendran;Dhireesha Kudithipudi;Shih-Chii Liu;Yao-Hong Liu;Haoyuan Ma;Rajit Manohar;Josep Maria Margarit-Taulé;Christian Mayr;Konstantinos Michmizos;Dylan R. Muir;Emre Neftci;Thomas Nowotny;Fabrizio Ottati;Ayca Ozcelikkale;Priyadarshini Panda;Jongkil Park;Melika Payvand;Christian Pehle;Mihai A. Petrovici;Christoph Posch;Alpha Renner;Yulia Sandamirskaya;Clemens J. S. Schaefer;André van Schaik;Johannes Schemmel;Samuel Schmidgall;Catherine Schuman;Jae-sun Seo;Sadique Sheik;Sumit Bam Shrestha;Manolis Sifalakis;Amos Sironi;Kenneth Stewart;Matthew Stewart;Terrence C. Stewart;Jonathan Timcheck;Nergis Tömen;Gianvito Urgese;Marian Verhelst;Craig M. Vineyard;Bernhard Vogginger;Amirreza Yousefzadeh;Fatima Tuz Zohora;Charlotte Frenkel;Vijay Janapa Reddi
  • 通讯作者:
    Vijay Janapa Reddi
Comparative Analysis of Passive, Active, and Hybrid Active Filters for Power Quality Improvement in Grid-Connected Photovoltaic System
无源、有源和混合有源滤波器改善并网光伏系统电能质量的比较分析
A 0.57 mm2 Platform with 70.7% Efficient 4 mA 3.2 V Charge Pump and a Current-Input Ramp ADC for Implantable Optical Sensing of Tumors
A%200.57%20mm2%20平台%20和%2070.7%%20效率%204%20mA%203.2%20V%20充电%20泵%20和%20a%20电流输入%20斜坡%20ADC%20用于%20植入%20光学%20传感%20of%20肿瘤

Siddharth Joshi的其他文献

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{{ truncateString('Siddharth Joshi', 18)}}的其他基金

CAREER: SHF: Bio-Inspired Microsystems for Energy-Efficient Real-Time Sensing, Decision, and Adaptation
职业:SHF:用于节能实时传感、决策和适应的仿生微系统
  • 批准号:
    2340799
  • 财政年份:
    2024
  • 资助金额:
    $ 29.96万
  • 项目类别:
    Continuing Grant

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  • 批准号:
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EAGER: SARE: In-Sensor Hardware-Software Co-design Methodology of the Hall Effect Sensors to Prevent and Contain the EMI Spoofing Attacks in the Analog-RF Systems
EAGER:SARE:霍尔效应传感器的传感器内硬件-软件协同设计方法,用于防止和遏制模拟射频系统中的 EMI 欺骗攻击
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SaTC: CORE: Small: Wireless Hardware Analog Encryption for Secure, Ultra Low Power Transmission of Data
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Hardware implementation and applications of analog high-dimensional neural system using simultaneous perturbation learning
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  • 财政年份:
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