EAGER: Exploring the Negative Capacitance Effect from Hf-Based Ferroelectrics and 2D Nanomaterials for Low-Voltage Transistors

EAGER：探索低压晶体管中铪基铁电体和二维纳米材料的负电容效应

• 批准号: 1656240
• 负责人: Aaron Franklin
• 金额: $ 15万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-10-01 至 2019-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1656240&HistoricalAwards=false
• 关键词: EAGER; Exploring; Negative; Capacitance; Effect

Transistors are the heartbeat of every electronic device, providing the connection between users and their data. As the size of transistors has continued to shrink based on Moore's Law, their use by the billions in computer chips has correspondingly soared. Amidst all of this scaling, the operating voltage has remained essentially constant for more than a decade, having major ramifications on the amount of electrical power used for computing. In this project, a new type of transistor will be demonstrated that brings together two-dimensional (2D) nanomaterials and ferroelectrics. The nanomaterials are superb electronic materials for very small devices and the ferroelectrics make possible a phenomenon known as negative capacitance. It is hypothesized that the marriage of these two advances will yield transistors that can operate at extremely low voltages. Such low voltage transistors could usher in a new era of "More than Moore" computing, such as reducing the power consumption in data centers, which are run by high-performance transistors, to address the national need for energy efficiency by offering a "green" data center solution. Additionally, there will be scientific learning regarding the use of ferroelectrics with nanomaterials that will drive a variety of new research directions. This project will also be impactful in promoting educational diversity, as a female graduate student along with a Latino graduate student, who is a NSF Graduate Research Fellow, will carry it out. Further, the extensive interest in nanomaterials among high school and undergraduate students makes this project ideal for attracting involvement of other underrepresented minorities around Duke through both established and new outreach programs. One promising option for overcoming the significant power problem in silicon transistors is to use the negative capacitance (NC) behavior of ferroelectric (FE) insulators to lower the operating voltage by amplifying the applied gate potential. In the last three years, a substantial uptick in research activity involving NC field-effect transistors (NC-FETs) has occurred, largely due to the demonstration that strong FE behavior can be achieved in appropriately synthesized, hafnium zirconium oxide (HfZrO2) thin films. However, NC-FETs with bulk semiconductor channels suffer from poor interface quality to the FE, a lack of device scalability due to thick FE layers, and a voltage-dependent substrate capacitance that results in drive currents that are orders of magnitude lower than traditional transistors. In this project, a possible solution to these challenges for extremely low-voltage NC-FETs will be explored by using the unique electrical and structural properties of 2D MoS2 in the gate stack to yield 2D NC-FETs. The primary goal of the project will be to demonstrate that the unique combination of a 2D channel with HfZrO2 ferroelectrics can yield sub-60 mV/decade switching (operation below the thermal limit). Several distinct approaches will be studied, including advancements in the atomic layer deposition synthesis and capping of the ferroelectric as well as transfer and contacting strategies for the 2D channel, in order to realize a 2D NC-FET that exhibits gate voltage amplification. While there is considerable work in the field on NC-FETs as well as transistors from 2D MoS2, bringing these distinct areas of research together in this device is highly distinct and potentially disruptive. Successful demonstration of a low power, high-performance 2D NC-FET will open the way for more extensive studies and programs that research the unique aspects of this device in greater depth.

晶体管是每个电子设备的心脏，提供用户与其数据之间的连接。 随着晶体管的尺寸根据摩尔定律不断缩小，它们在计算机芯片中的使用量也相应激增。 在所有这些缩放中，工作电压在十多年内基本保持不变，对计算所用的电力量产生了重大影响。 在这个项目中，将展示一种新型的晶体管，它将二维（2D）纳米材料和铁电材料结合在一起。 纳米材料是非常小的设备的极好的电子材料，铁电体使负电容现象成为可能。 据推测，这两种进步的结合将产生可以在极低电压下工作的晶体管。 这种低电压晶体管可以开创“超过摩尔”计算的新时代，例如通过提供“绿色”数据中心解决方案来降低由高性能晶体管运行的数据中心的功耗，以解决国家对能源效率的需求。 此外，将有关于使用铁电体与纳米材料的科学学习，这将推动各种新的研究方向。 该项目还将对促进教育多样性产生影响，因为一名女研究生将沿着一名拉丁裔研究生（NSF研究生研究员）执行该项目。 此外，高中和本科生对纳米材料的广泛兴趣使该项目成为吸引杜克周围其他代表性不足的少数民族参与的理想选择。克服硅晶体管中的显著功率问题的一个有希望的选择是使用铁电（FE）绝缘体的负电容（NC）行为来通过放大所施加的栅极电势来降低操作电压。 在过去的三年中，涉及NC场效应晶体管（NC-FET）的研究活动大幅上升，这主要是由于证明了在适当合成的铪锆氧化物（HfZrO 2）薄膜中可以实现强FE行为。 然而，具有体半导体沟道的NC-FET遭受到FE的界面质量差、由于厚FE层而缺乏器件可扩展性、以及导致驱动电流比传统晶体管低几个数量级的电压依赖性衬底电容。 在这个项目中，极低电压NC-FET的这些挑战的一个可能的解决方案将通过在栅极叠层中使用2D MoS 2的独特电气和结构特性来产生2D NC-FET来探索。 该项目的主要目标是证明2D通道与HfZrO 2铁电体的独特组合可以产生低于60 mV/十倍的开关（在热极限以下运行）。 将研究几种不同的方法，包括原子层沉积合成和铁电体的覆盖以及2D沟道的传输和接触策略的进步，以实现具有栅极电压放大的2D NC-FET。 虽然在NC-FET和2D MoS 2晶体管领域有大量的工作，但将这些不同的研究领域结合在一起是非常独特的，并且可能具有破坏性。 低功耗、高性能2D NC-FET的成功演示将为更深入地研究该器件独特方面的更广泛的研究和计划开辟道路。

项目成果

Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs

• DOI: 10.1109/jeds.2019.2922441
• 发表时间: 2019-06
• 期刊: IEEE Journal of the Electron Devices Society
• 影响因子: 2.3
• 作者: Yuh-Chen Lin;Felicia A. McGuire;Steven G. Noyce;Nicholas X. Williams;Zhihui Cheng;J. Andrews;A. Franklin