1D Edge Contacts to 2D Devices for Scalability and 3D Integration with Via-formed Junctions

1D 边缘触点与 2D 器件的可扩展性以及与通孔形成结的 3D 集成

• 批准号: 1915814
• 负责人: Aaron Franklin
• 金额: $ 39.07万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-07-01 至 2022-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1915814&HistoricalAwards=false
• 关键词: 1D; Edge; Contacts; 2D; Devices

Nontechnical:Two-dimensional (2D) semiconductors have the potential to be scaled to small dimensions and integrated in versatile ways. There are, however, significant challenges to realize reproducible, scalable, and high-performance electronics based on 2D materials. This project will explore a new approach by fabricating one-dimensional (1D) edge contacts to 2D materials to improve scalability. All electrical current passes between the contact and the 2D material along a 1D edge. This will boost performance over devices with top contacts. 1D edge contacts have an advantage in that they will enable three-dimensional (3D) integration of 2D devices into integrated circuits. An advantage of this approach is that 3D circuits can be realized with fewer fabrication steps than traditionally required. 3D integration of devices has the potential to impact energy efficient computing. Research into electrical transport at 1D edge contacts will also be of widespread value to the electronics community. This project will actively engage women and underrepresented minorities in research activities. Outreach will continue throughout the project through existing and new activities that will engage K-12 and undergraduate students.Technical:Integration of 2D materials into future electronics requires understanding of carrier transport, scalability, and integration. Edge contacts offer improved transport over top contacts, yet they lack rigorous study for 2D devices and the mechanism of carrier injection at the metal-2D edge interface remains unclear. While 2D materials have no surface states for interfacial bonding, they do have abundant dangling bonds at the edge, which could be harnessed to improve interfacial electron transport. Building on the PI's preliminary results of the first pure edge contacts to a 2D semiconductor, the carrier transport of 1D edge contacts to 2D devices will be studied in this project, from material preparation and device fabrication, to performance characterization and 3D integration. Uncovering the mechanisms of carrier transport at 1D metal to 2D semiconductor junctions will be done by studying pure edge interfaces realized with an in situ ion beam / evaporator for generating the 2D edge and establishing the 1D contact without breaking high vacuum. Two distinct uses of edge contacts will be demonstrated: 1) Scalability of contacts to the sub-10 nm dimensions without compromising performance, and 2) 3D integration of 2D devices made more feasible with via-formed junctions that double as 1D edge contacts. Large sets of top- and edge-contacted devices will be studied across a range of contact lengths and for three different 2D materials. For 3D integration of 2D devices in the back-end of the line (BEOL), no viable contact strategy is available that will not significantly increase mask layers and thus production cost. This demonstration of edge contacts to 2D devices established in the same processing step as contact via formation, will be achieved using a single mask layer. This strategy for 3D-integrated 2D devices with via-formed edge contacts will be of significant benefit to the growing area of BEOL nanodevice integration.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

非技术性：二维（2D）半导体有可能被缩小到小尺寸，并以多种方式集成。然而，要实现基于2D材料的可再现、可扩展和高性能电子器件，存在重大挑战。该项目将探索一种新的方法，通过制造一维（1D）边缘接触到2D材料，以提高可扩展性。所有电流都沿沿着1D边在触点和2D材料之间通过。这将提高具有顶部触点的设备的性能。1D边缘接触的优点在于它们将使得能够将2D器件三维（3D）集成到集成电路中。这种方法的优点在于，可以用比传统所需更少的制造步骤来实现3D电路。设备的3D集成有可能影响节能计算。在一维边缘接触的电输运的研究也将具有广泛的价值，以电子社区。这一项目将使妇女和代表性不足的少数群体积极参与研究活动。通过现有的和新的活动，将继续在整个项目中进行推广，这些活动将吸引K-12和本科生。技术：将2D材料集成到未来的电子产品中需要了解载体传输，可扩展性和集成。边缘接触提供了改善的顶部接触的传输，但他们缺乏严格的研究，在金属-2D边缘界面的载流子注入的机制仍然不清楚。虽然2D材料没有界面键合的表面态，但它们在边缘确实有丰富的悬挂键，可以利用这些悬挂键来改善界面电子传输。基于PI的第一个纯边缘接触到2D半导体的初步结果，该项目将研究1D边缘接触到2D器件的载流子传输，从材料制备和器件制造，到性能表征和3D集成。通过研究用原位离子束/蒸发器实现的纯边缘界面来揭示一维金属到二维半导体结的载流子传输机制，该离子束/蒸发器用于生成二维边缘并在不破坏高真空的情况下建立一维接触。 边缘接触的两种不同用途将被证明：1）接触到亚10 nm尺寸的可扩展性，而不影响性能，2）2D器件的3D集成与通孔形成的结，加倍作为1D边缘接触更可行。将在一系列接触长度和三种不同的2D材料中研究大型顶部和边缘接触器械。对于生产线后端（BEOL）中的2D器件的3D集成，没有可行的接触策略可用，其不会显著增加掩模层并因此增加生产成本。在与接触通孔形成相同的处理步骤中建立的到2D器件的边缘接触的这种演示将使用单个掩模层来实现。这种具有通孔形成边缘接触的3D集成2D设备的策略将对BEOL纳米设备集成的不断增长的领域产生显着的好处。该奖项反映了NSF的法定使命，并且通过使用基金会的智力价值进行评估，被认为值得支持和更广泛的影响审查标准。

项目成果

Short-channel robustness from negative capacitance in 2D NC-FETs

• DOI: 10.1063/5.0030555
• 发表时间: 2021-03
• 期刊: Applied Physics Letters
• 影响因子: 4
• 作者: Yuh-Chen Lin;G. Rayner;Jorge A. Cardenas;A. Franklin

How to report and benchmark emerging field-effect transistors

• DOI: 10.1038/s41928-022-00798-8
• 发表时间: 2022-07-01
• 期刊: NATURE ELECTRONICS
• 影响因子: 34.3
• 作者: Cheng, Zhihui;Pang, Chin-Sheng;Richter, Curt A.
• 通讯作者: Richter, Curt A.

How good are 2D transistors? An application-specific benchmarking study

• DOI: 10.1063/5.0029712
• 发表时间: 2021-01-18
• 期刊: APPLIED PHYSICS LETTERS
• 影响因子: 4
• 作者: Abuzaid, Hattan;Williams, Nicholas X.;Franklin, Aaron D.
• 通讯作者: Franklin, Aaron D.

Unanticipated Polarity Shift in Edge-Contacted Tungsten-Based 2D Transition Metal Dichalcogenide Transistors

• DOI: 10.1109/led.2021.3106286
• 发表时间: 2021-10-01
• 期刊: IEEE ELECTRON DEVICE LETTERS
• 影响因子: 4.9
• 作者: Abuzaid, Hattan;Cheng, Zhihui;Franklin, Aaron D.
• 通讯作者: Franklin, Aaron D.

Are 2D Interfaces Really Flat?

• DOI: 10.1021/acsnano.1c11493
• 发表时间: 2022-03
• 期刊: ACS nano
• 影响因子: 17.1
• 作者: Zhihui Cheng;Huairuo Zhang;S. Le;Hattan Abuzaid;Guoqing Li;Linyou Cao;A. Davydov;A. Franklin