1D Edge Contacts to 2D Devices for Scalability and 3D Integration with Via-formed Junctions

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Nontechnical:Two-dimensional (2D) semiconductors have the potential to be scaled to small dimensions and integrated in versatile ways. There are, however, significant challenges to realize reproducible, scalable, and high-performance electronics based on 2D materials. This project will explore a new approach by fabricating one-dimensional (1D) edge contacts to 2D materials to improve scalability. All electrical current passes between the contact and the 2D material along a 1D edge. This will boost performance over devices with top contacts. 1D edge contacts have an advantage in that they will enable three-dimensional (3D) integration of 2D devices into integrated circuits. An advantage of this approach is that 3D circuits can be realized with fewer fabrication steps than traditionally required. 3D integration of devices has the potential to impact energy efficient computing. Research into electrical transport at 1D edge contacts will also be of widespread value to the electronics community. This project will actively engage women and underrepresented minorities in research activities. Outreach will continue throughout the project through existing and new activities that will engage K-12 and undergraduate students.Technical:Integration of 2D materials into future electronics requires understanding of carrier transport, scalability, and integration. Edge contacts offer improved transport over top contacts, yet they lack rigorous study for 2D devices and the mechanism of carrier injection at the metal-2D edge interface remains unclear. While 2D materials have no surface states for interfacial bonding, they do have abundant dangling bonds at the edge, which could be harnessed to improve interfacial electron transport. Building on the PI's preliminary results of the first pure edge contacts to a 2D semiconductor, the carrier transport of 1D edge contacts to 2D devices will be studied in this project, from material preparation and device fabrication, to performance characterization and 3D integration. Uncovering the mechanisms of carrier transport at 1D metal to 2D semiconductor junctions will be done by studying pure edge interfaces realized with an in situ ion beam / evaporator for generating the 2D edge and establishing the 1D contact without breaking high vacuum. Two distinct uses of edge contacts will be demonstrated: 1) Scalability of contacts to the sub-10 nm dimensions without compromising performance, and 2) 3D integration of 2D devices made more feasible with via-formed junctions that double as 1D edge contacts. Large sets of top- and edge-contacted devices will be studied across a range of contact lengths and for three different 2D materials. For 3D integration of 2D devices in the back-end of the line (BEOL), no viable contact strategy is available that will not significantly increase mask layers and thus production cost. This demonstration of edge contacts to 2D devices established in the same processing step as contact via formation, will be achieved using a single mask layer. This strategy for 3D-integrated 2D devices with via-formed edge contacts will be of significant benefit to the growing area of BEOL nanodevice integration.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.