CRII: SHF: Improving Programmability of GPGPU/NVRAM Integrated Systems with Holistic Architectural Support

在大数据时代，行业面临着对更高计算能力和大容量高性能存储的日益增长的需求。GPGPU和NVRAM是两项突出的技术，将在“大数据革命”中发挥关键作用。该项目从整体上提高了GPGPU/NVRAM集成系统的可编程性，解决了GPGPU和NVRAM所面临的可编程性瓶颈。这将使在高性能的GPGPU和NVRAM中开发正确的应用程序变得更容易。因此，该项目将推动将GPGPU和NVRAM应用于广泛的HPC和大数据应用程序的愿望，这些应用程序可以在确保可恢复性的同时获得数百倍的加速。总体而言，该项目的成果将有助于确保可持续的性能，以支持科学和工程(如金融、医学、生物、石油、航空航天和地质)的超级计算/大数据处理。该项目还将通过吸引少数族裔服务机构的高中生和本科生参与研究，吸引女性和代表不足的群体进入研究生教育，利用GPGPU/NVRAM架构扩展计算机工程课程，传播用于教育和培训的研究基础设施，以及与行业合作，为社会做出贡献。本研究探讨了通过以下技术全面提高GPGPU/NVRAM集成系统可编程性的协同方法和技术：(1)基于时间戳的GPU一致性协议。它通过不存储共享状态(例如，共享、修改、独占等)来避免存储开销和分享者的名单。它通过不发送显式无效消息来减少流量开销。(2)持久化与作用域同步的结合。本研究旨在研究持久化作用域的新概念，它将必要的持久化语义融入到现有的GPGPU编程模型中的作用域同步中。将探索完全分离一致性和持久性的高效体系结构设计。(3)支持数据共享的CTA调度器和缓存管理。这项研究计划研究一种共享感知的CTA调度器，该调度器试图将具有数据共享的CTA分配给相同的SM，以改善时间和空间局部性。

In the era of big data, the industry faces growing demand for higher computing power and large-capacity high performance storage. GPGPU and NVRAM are two prominent technologies that will play the key role in the "Big Data revolution". This project, which holistically improves the programmability of GPGPU/NVRAM integrated systems, tackles the "programmability bottleneck" faced in GPGPU and NVRAM. It will make it easier to develop correct applications in GPGPU and NVRAM with high performance. As a result, the project will enforce the desire of applying GPGPUs and NVRAM into a wide-range of HPC and big data applications which could then gain hundreds times speedup while ensuring recoverability. Overall, the outcomes of this project will help ensure the sustainable performance to support the supercomputing/big data processing in science and engineering (e.g. finance, medical, biology, petroleum, aerospace, and geology). This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions into research, attracting women and under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU/NVRAM architectures, disseminating research infrastructure for education and training, and collaborating with the industry.This research investigates synergetic approaches and techniques to holistically improve the programmability of GPGPU/NVRAM integrated systems with the following techniques: (1) Timestamp-Based GPU Coherence Protocol. It avoids storage overhead by not storing sharing states (e.g. Shared, Modified, Exclusive, etc.) and the list of sharers. It reduces the traffic overhead by not sending explicit invalidation messages. (2) Integration of Persistency and the Scoped-Synchronization. This research aims to study the new notion of Persistent Scope (PS) , which incorporates the necessary persistency semantics into the existing scoped-synchronization in GPGPU programming models. Efficient architecture design that fully decouples consistency and persistency will be explored. (3) Data Sharing-Aware CTA Scheduler and Cache Management. This research plans to investigate a sharing-aware CTA scheduler that attempts to assign CTAs with data sharing to the same SM to improve temporal and spatial locality.