SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability

SHF：中：协作研究：支持机器学习的片上网络架构，可优化能源、性能和可靠性

• 批准号: 1702496
• 负责人: D Brian Ma
• 金额: $ 25万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-06-01 至 2021-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1702496&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; Machine

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community's design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.

片上网络（NoC）架构已经成为多核和芯片多处理器（cmp）的主流片上通信结构。然而，随着NoC架构的扩展，它们面临着严峻的挑战。当今优化NoC架构设计的一个关键挑战是NoC设计人员可用的大量性能增强、节能和容错技术，以及必须同时导航的大型设计空间，以降低功耗、提高可靠性、提高性能和保持QoS。本研究提出了一种新的跨层、跨领域的方法，涵盖电路、架构、机器学习算法和应用，旨在设计节能、可靠和可扩展的noc。这项研究将产生(1)新颖的跨层设计技术，采用整体方法同时降低功耗，同时仍能实现NoC的可靠性和性能目标；(2)对使用硬件兼容的ML进行NoC设计优化的基本理解；(3)在网络执行过程中监测和收集关键数据和关键设计参数的软硬件技术，以优化NoC设计。(4)建模和仿真工具，这些工具将改进架构社区评估可扩展noc的设计方法。这项提议的研究弥合了硬件架构师和机器学习科学家之间非常重要的鸿沟，硬件架构师在电路和架构级别设计电源管理和容错技术，机器学习科学家开发预测和优化技术。由于其跨领域的性质，拟议的研究有可能显著改变下一代cmp和片上系统（soc）的设计，在这些设计中，必须做出影响功率、性能和可靠性的复杂决策。这项研究还将通过将发现与教学和培训结合起来，在教育方面发挥重要作用。国家警察承诺并将继续扩大外联活动，作为拟议项目的一部分，为此作出必要努力，吸引和培训这一领域的少数民族学生。

项目成果

18.1 A Self-Health-Learning GaN Power Converter Using On-Die Logarithm-Based Analog SGD Supervised Learning and Online T j -Independent Precursor Measurement

18.1 使用基于片内对数的模拟 SGD 监督学习和在线 T j 独立前体测量的自健康学习 GaN 功率转换器

• DOI: 10.1109/isscc19947.2020.9062999
• 发表时间: 2020
• 期刊: 2020 IEEE International Solid- State Circuits Conference - (ISSCC
• 作者: Huang, Yuanqing;Chen, Yingping;Ma, D. Brian
• 通讯作者: Ma, D. Brian

EMI-Regulated GaN-Based Switching Power Converter With Markov Continuous Random Spread-Spectrum Modulation and One-Cycle on-Time Rebalancing

具有马尔可夫连续随机扩频调制和单周期准时再平衡功能的 EMI 调节 GaN 开关电源转换器

• DOI: 10.1109/jssc.2019.2931439
• 发表时间: 2019
• 期刊: IEEE Journal of Solid-State Circuits
• 影响因子: 5.4
• 作者: Chen, Yingping;Ma, D. Brian
• 通讯作者: Ma, D. Brian

DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning

DozzNoC：利用机器学习通过低延迟稳压器减少 NoC 中的静态和动态能量

• DOI: 10.1109/ipdps47924.2020.00011
• 发表时间: 2020
• 期刊: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS
• 作者: Clark, Mark;Chen, Yingping;Karanth, Avinash;Ma, Brian;Louri, Ahmed
• 通讯作者: Louri, Ahmed