Real100G.com: Mixed Mode Baseband for 100 Gbps Wireless Communication

Real100G.com项目旨在实现100 Gbps无线通信，具有超高射频带宽（50 GHz）、中等频谱效率（2至4 b/s/Hz）以及240 GHz左右高毫米波频率的载波频率。我们在第一阶段和第二阶段都采用这种系统方法，重点是系统设计研究、基带信号处理和同步。未来所有 100 Gbps 无线系统的主要挑战将是基带处理器的极端信号处理能力、复杂性和功耗。此外，在我们的方法中，超高射频带宽的使用导致了基带处理器的极端带宽要求（25 GHz）。我们的研究重点是模拟/混合信号基带处理，并基于这样的假设：模拟和数字信号处理的智能混合在功耗、硬件复杂性以及最终成本方面有可能超越纯数字信号处理。我们选择并行扩频排序 (PSSS) 作为模拟友好的调制和编码方案，可实现 100 Gbps 无线基带处理器的高效模拟/混合信号实现。此外，出于类似的原因，人们还研究了模拟/混合信号射频同步方案。在第一阶段，我们重点关注 100 Gbps PSSS 系统设计、PSSS 接收器基带处理器设计和 RF 同步。我们已经成功演示了 240 GHz 载波频率下的 40 Gbps PSSS 调制数据传输，并验证了混合信号基带处理器的核心电路和硬件同步方案。在 SPP 的第二阶段，我们希望继续这条成功之路，并向我们的 100 Gbps 收发器添加新组件，例如。 g。 PSSS 发射机基带处理器。此外，我们在第一阶段的研究中出现了一些有趣的新主题，例如对 PSSS 信号削波和频谱整形的研究，以及替代同步技术。我们计划继续与 Real100G.rf（Zwick、Pfeiffer）和 End2End100（Nolte、Kraemer）项目合作，这些项​​目已经完成了总体系统设计，并希望在 SPP 第二阶段结束时进行扩展联合传输实验，目标​​是实现完整的 100 Gbps 无线系统演示。

The project Real100G.com aims at achieving 100 Gbps wireless communication with an ultra-high RF bandwidth (50 GHz), moderate spectral efficiency (2 to 4 b/s/Hz), and a carrier frequency at high millimeter-wave frequencies around 240 GHz. We pursue this system approach for both first and second phase, focusing on system design investigations, baseband signal processing, and synchronization. Major challenges of all future 100 Gbps wireless systems will be the extreme signal processing power, complexity, and power dissipation of the baseband processor. Furthermore, in our approach the use of ultra-high RF bandwidth results in extreme bandwidth requirements (25 GHz) for the baseband processor. Our research focuses on analog/mixed-signal baseband processing and is based on the assumption that an intelligent mixture of analog and digital signal processing has the potential to outperform purely digital signal processing in terms of power dissipation and hardware complexity and eventually cost. We chose Parallel-Spread-Spectrum Sequencing (PSSS) as an analog-friendly modulation and coding scheme that allows for an efficient analog/mixed-signal implementation of a 100 Gbps wireless baseband processor. Furthermore, analog/mixed-signal RF synchronization schemes are investigated for similar reasons. In the first phase we have focused on 100 Gbps PSSS system design, PSSS receiver baseband processor design, and RF synchronization. We already successfully demonstrated 40 Gbps PSSS-modulated data transmission at 240 GHz carrier frequency and validated core circuits of our mixed-signal baseband processor and synchronization scheme in hardware. In the second phase of the SPP we want to continue this successful path and add new components to our 100 Gbps transceiver, e. g. the PSSS transmitter baseband processor. Furthermore, some interesting new topics emerged from our research in the first phase such as investigations on PSSS signal clipping and spectral shaping, as well as alternative synchronization techniques. We plan to continue our cooperation with the projects Real100G.rf (Zwick, Pfeiffer) and End2End100 (Nolte, Kraemer) which resulted already in an overall system design and want to perform extended joint transmission experiments at the end of the 2nd phase of the SPP targeting for a complete 100 Gbps wireless system demonstration.