Design Method for Digital Logic Circuits with Optimization for Dependability and Life Time

可靠性和寿命优化的数字逻辑电路设计方法

• 批准号: 239166496
• 负责人: Professor Dr.-Ing. Heinrich Theodor Vierhaus
• 金额: --
• 依托单位: Fachgebiet Technische Informatik
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2013
• 资助国家: 德国
• 起止时间: 2012-12-31 至 2016-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/239166496?language=en
• 关键词: Design; Method; Digital; Logic; Circuits

Integrated circuits and systems, based on nano-technologies, have shown a rising level of vulnerability with respect to transient fault effects on one side and permanent faults due to early wear-out on the other hand. Technologies of fault tolerant computing have been known for a long time, but they are in most cases costly in terms of devices and power consumption, or they are applicable only to specific types of faults. Technologies of built-in self repair for logic have found little practical application so far. The project targets a systematic introduction of on-line test, fault tolerance and even self repair into digital system design, depending on the specific demands for individual circuits, signals and sub-systems. This means a new step in design technology, which has to be as compatible as possible with standards in tools and design flows. Finally, the project will, for the first time, achieve an optimized combination of on-line-test and error correction and self repair for life-time extension at affordable cost.

以纳米技术为基础的集成电路和系统，一方面易受瞬时故障影响，另一方面易受早期磨损造成的永久性故障影响，从而显示出越来越大的脆弱性。容错计算的技术已经知道很长时间了，但是它们在大多数情况下在设备和功耗方面是昂贵的，或者它们仅适用于特定类型的故障。到目前为止，逻辑的内建自修复技术几乎没有实际应用。该项目的目标是根据各个电路、信号和子系统的具体要求，在数字系统设计中系统地引入在线测试、容错甚至自我修复。这意味着设计技术的一个新台阶，它必须尽可能与工具和设计流程中的标准兼容。最后，该项目将首次实现在线测试、纠错和自修复的优化组合，以合理的成本延长寿命。

项目成果

An Interactive Design Space Exploration Tool for Dependable Integrated Circuits

• DOI: 10.1109/dsd.2016.83
• 发表时间: 2016-08
• 期刊: 2016 Euromicro Conference on Digital System Design (DSD)
• 作者: Stefan Scharoba;H. Vierhaus

Fast power overhead prediction for hardware redundancy-based fault tolerance

基于硬件冗余的容错的快速功率开销预测

• DOI: 10.1109/iolts.2017.8046232
• 发表时间: 2017
• 期刊: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)
• 作者: S. Scharoba;H. T. Vierhaus
• 通讯作者: H. T. Vierhaus

On reliability estimation for combined transient and permanent fault handling

结合瞬态和永久性故障处理的可靠性估计

• DOI: 10.1109/bec.2014.7320559
• 发表时间: 2014
• 期刊: 2014 14th Biennial Baltic Electronic Conference (BEC)
• 作者: S. Scharoba;M. Schölzel;T. Koal;H.T. Vierhaus
• 通讯作者: H.T. Vierhaus

Combining Correction of Delay Faults and Transient Faults

延时故障与瞬态故障相结合的修复

• DOI: 10.1109/ddecs.2015.23
• 发表时间: 2015
• 期刊: 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
• 作者: T. Koal;S. Scharoba;H. T. Vierhaus
• 通讯作者: H. T. Vierhaus