Design Method for Digital Logic Circuits with Optimization for Dependability and Life Time

点击翻译按钮获取中文摘要

Integrated circuits and systems, based on nano-technologies, have shown a rising level of vulnerability with respect to transient fault effects on one side and permanent faults due to early wear-out on the other hand. Technologies of fault tolerant computing have been known for a long time, but they are in most cases costly in terms of devices and power consumption, or they are applicable only to specific types of faults. Technologies of built-in self repair for logic have found little practical application so far. The project targets a systematic introduction of on-line test, fault tolerance and even self repair into digital system design, depending on the specific demands for individual circuits, signals and sub-systems. This means a new step in design technology, which has to be as compatible as possible with standards in tools and design flows. Finally, the project will, for the first time, achieve an optimized combination of on-line-test and error correction and self repair for life-time extension at affordable cost.