CAREER: Regulator-Gating (ReGa): A New On-Chip Power Delivery Architecture

随着半导体工业的不断进步，具有小于20 nm特征尺寸的晶体管已经能够在单个管芯上集成数十亿个晶体管。在任何给定时间，大部分电路块要么是不活动的，要么处于降低功率状态，以满足功率和热约束。这种利用率墙促使半导体界妥协芯片面积和电路速度，以降低整体功耗。尽管对整体功率优化技术进行了大量的研究和日益增长的必要性，但是现有的使功率耗散最小化的努力通常是不一致的，并且被分成两部分：i）使负载电路处的动态和静态功率损耗最小化，或者ii）使功率转换期间的功率损耗最小化。因此，在现代移动的平台中，超过32%的总功率甚至在到达负载电路之前就在高到低电压转换期间耗散。无论是PI的初步工作，还是以前的研究都没有提出一个整体的方法来设计和管理分布式片上电源传输，并且对于实现高的整体电压转换效率和热感知设计的作用有限。本项目的最终目标是重新审视并从根本上定制片上电源传输基础设施的设计和管理。与传统的方案相比，其中电源网络的设计目标是充分利用整个芯片面积，所提出的研究将提供一个自适应的电力输送基础设施，该基础设施是定制的，以提供高电压转换效率在充分利用和未充分利用的操作模式。新的电压调节技术和支持电路，电力输送网络的物理设计，以及电源管理方案将被提出。具体重点将放在并联电压调节和交付的分配，大小和类型的个别监管机构进行优化，考虑各种可能的权衡协同。调节器门控将专门用于：i）迫使各个电压调节器在其最省电的区域内工作，ii）分散导致局部热点的集中热量，以及iii）打开靠近有源电路的电压调节器以降低噪声。该项目的研究部分对与晶闸管相关的研究的所有子领域具有广泛的影响，因为功率效率已成为主要瓶颈。该项目的教育部分将提供指导方针，说明如何将不同的教学技术整合到本科和研究生课程中，以加强工程教育。PI将促进妇女和代表性不足的少数民族参与STEM领域，并与当地一所历史悠久的黑人大学建立牢固的联系，以增加南佛罗里达大学电气工程系代表性不足的少数民族的入学人数。

With continuous advancements in the semiconductor industry, transistors with smaller than 20 nm feature size have enabled the integration of multi-billion transistors on a single die. A large proportion of the circuit blocks is either inactive or in a reduced-power state at any given time to satisfy the power and thermal constraints. This utilization wall has urged the semiconductor community to compromise the chip area and the speed of the circuit to reduce the overall power consumption. Despite the significant amount of research and growing necessity for a holistic power optimization technique, existing efforts to minimize power dissipation are typically not coherent and are disjointed into two pieces: i) the dynamic and static power loss at the load circuits is minimized or ii) the power loss during power-conversion is minimized. As a result, more than 32% of the overall power is dissipated during high-to-low voltage conversion before even reaching the load circuits in modern mobile platforms. Neither the preliminary works of the PI nor the previous studies present a holistic approach for the design and management of distributed on-chip power delivery and are of limited use to attain high overall voltage conversion efficiency and thermal-aware design.The ultimate goal of this project is to revisit and fundamentally tailor the design and management of on-chip power delivery infrastructure. As compared to the conventional schemes where the power network is designed targeting the full utilization of the overall chip area, the proposed research will provide an adaptive power delivery infrastructure that is tailored to provide high voltage conversion efficiency during both fully-utilized and under-utilized modes of operation. Novel voltage regulation techniques and support circuits, physical design of power delivery networks, and power management schemes will be proposed. Specific emphasis will be placed on parallel voltage regulation and delivery where the allocation, size, and type of individual regulators are optimized synergistically considering various possible tradeoffs. Regulator-gating will be used specifically to: i) force individual voltage regulators to operate in their most power-efficient region, ii) spread the concentrated heat that causes local hotspots, and iii) turn on the voltage regulators close to the active circuits to reduce noise. The research component of this project has broad implications across all sub-areas of semiconductor-related research as power efficiency has become the primary bottleneck. The education component of this project will provide guidelines on how different teaching techniques can be integrated in undergraduate and graduate level courses to enhance the engineering education. The PI will promote the participation of women and underrepresented minorities in STEM fields and build strong ties with a local historically black college to increase the enrollment of underrepresented minorities at the University of South Florida's Electrical Engineering Department.