CAREER: Regulator-Gating (ReGa): A New On-Chip Power Delivery Architecture

随着半导体工业的不断进步，小于20nm特征尺寸的晶体管已经能够在单个芯片上集成数十亿个晶体管。大部分电路块在任何给定时间都处于非活动状态或低功耗状态，以满足功率和热约束。这种利用壁垒促使半导体界在芯片面积和电路速度上做出妥协，以降低整体功耗。尽管对整体功率优化技术进行了大量的研究和日益增长的需求，但现有的最小化功耗的努力通常是不连贯的，并且分为两部分：i)最小化负载电路中的动态和静态功率损耗或ii)最小化功率转换过程中的功率损耗。因此，在现代移动平台中，甚至在到达负载电路之前，超过32%的总功率在高低电压转换期间耗散。PI的初步工作和先前的研究都没有提出分布式片上电源传输的设计和管理的整体方法，并且在实现高整体电压转换效率和热感知设计方面的用途有限。该项目的最终目标是重新审视并从根本上定制片上电力传输基础设施的设计和管理。与传统方案相比，电网的设计目标是充分利用整个芯片面积，拟议的研究将提供一个自适应的电力输送基础设施，在充分利用和未充分利用的运行模式下提供高电压转换效率。将提出新的电压调节技术和支持电路、电力输送网络的物理设计和电力管理方案。具体的重点将放在并联电压调节和输送，其中分配，大小和类型的个别稳压器被优化协同考虑各种可能的权衡。调节器门控将专门用于：i)迫使单个电压调节器在其最节能的区域工作，ii)传播引起局部热点的集中热量，以及iii)打开靠近有源电路的电压调节器以降低噪声。这个项目的研究部分在半导体相关研究的所有子领域具有广泛的意义，因为功率效率已经成为主要的瓶颈。该项目的教育部分将提供指导，说明如何将不同的教学技术整合到本科和研究生水平的课程中，以加强工程教育。该项目将促进女性和未被充分代表的少数族裔参与STEM领域，并与当地一所历史悠久的黑人学院建立牢固的联系，以增加南佛罗里达大学电气工程系未被充分代表的少数族裔的入学率。

With continuous advancements in the semiconductor industry, transistors with smaller than 20 nm feature size have enabled the integration of multi-billion transistors on a single die. A large proportion of the circuit blocks is either inactive or in a reduced-power state at any given time to satisfy the power and thermal constraints. This utilization wall has urged the semiconductor community to compromise the chip area and the speed of the circuit to reduce the overall power consumption. Despite the significant amount of research and growing necessity for a holistic power optimization technique, existing efforts to minimize power dissipation are typically not coherent and are disjointed into two pieces: i) the dynamic and static power loss at the load circuits is minimized or ii) the power loss during power-conversion is minimized. As a result, more than 32% of the overall power is dissipated during high-to-low voltage conversion before even reaching the load circuits in modern mobile platforms. Neither the preliminary works of the PI nor the previous studies present a holistic approach for the design and management of distributed on-chip power delivery and are of limited use to attain high overall voltage conversion efficiency and thermal-aware design.The ultimate goal of this project is to revisit and fundamentally tailor the design and management of on-chip power delivery infrastructure. As compared to the conventional schemes where the power network is designed targeting the full utilization of the overall chip area, the proposed research will provide an adaptive power delivery infrastructure that is tailored to provide high voltage conversion efficiency during both fully-utilized and under-utilized modes of operation. Novel voltage regulation techniques and support circuits, physical design of power delivery networks, and power management schemes will be proposed. Specific emphasis will be placed on parallel voltage regulation and delivery where the allocation, size, and type of individual regulators are optimized synergistically considering various possible tradeoffs. Regulator-gating will be used specifically to: i) force individual voltage regulators to operate in their most power-efficient region, ii) spread the concentrated heat that causes local hotspots, and iii) turn on the voltage regulators close to the active circuits to reduce noise. The research component of this project has broad implications across all sub-areas of semiconductor-related research as power efficiency has become the primary bottleneck. The education component of this project will provide guidelines on how different teaching techniques can be integrated in undergraduate and graduate level courses to enhance the engineering education. The PI will promote the participation of women and underrepresented minorities in STEM fields and build strong ties with a local historically black college to increase the enrollment of underrepresented minorities at the University of South Florida's Electrical Engineering Department.