Photonic Tensor Accelerators for Artificial Neural Networks

人工智能(AI)和人工神经网络(ANN)主导了关于科学、技术、经济、社会和文化，甚至人类本身的未来的对话。人工智能之所以令人兴奋，是因为它识别模式，甚至发现比基于人类智能的解决方案更好的解决方案。人工智能的快速发展在很大程度上归功于计算能力的增强。近年来，集成电路(IC)的计算能力已经不能维持按照摩尔定律的增长速度。硬件加速器具有专门为并行计算设计的处理单元和优化的内存体系结构，在机器学习(ML)模型的实现中发挥了关键作用。然而，电子硬件加速器在可扩展性方面已经被推到了极限，无法跟上数据量的指数增长。在这种背景下，在光传输的大带宽和低损耗的推动下，人们再次努力探索光学在计算中的作用。该项目提出了光子张量加速器(PTA)，这是一种能够进行矩阵-矢量乘法和矩阵-矩阵乘法的高度并行的光子体系结构，其计算能力比现有的电子加速器高出几个数量级。由于其高度的并行化，PTA特别适合于实现人工神经网络模型的批处理矩阵乘法。这项提案中开发的技术可以展示先进硬件和软件的协同作用，并吸引更多的学生进入与硬件相关的领域。这项研究本质上是跨学科的，可以作为美国教育部指定的西班牙裔服务机构UCF的研究生和本科生培训的平台。该项目的总体目标是构建光子加速器，使其1)提供比电子设备高出数量级的可扩展性，2)快速、可编程，与培训和推理完美兼容，3)降低功耗密度，使ANN能够与纯电子同行竞争。神经网络的核心是张量乘法，它只需要大规模的特殊运算(乘法和累加，而不是通用计算)，特别适合于光子加速器。此外，神经网络在非线性激活过程中对低动态范围的变化具有很强的鲁棒性。PTA利用光的所有自由度来加速张量相乘。具体地说，PTA利用信号与本机振荡器之间的相干拍频进行倍增、频率/波长、空间模式和极化积累，并利用自由空间的2-D和3-D并行来衡量处理能力。所提出的方法可以在包括图形处理单元(GPU)和诸如张量处理单元(TPU)之类的ASIC的最先进的IC硬件加速器上将乘法累加(MAC)运算的数量扩展几个数量级。该项目将重新调整循环回路的技术，以扩大深度神经网络(DNN)的层数。这项拟议的研究也与人工智能(AI)具有协同作用，因为一些新设备将使用机器学习技术设计，基于PTA的ANN的可用性允许新的ANN训练范例。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Artificial intelligence (AI) and artificial neural networks (ANNs) have dominated conversations about the future of science, technology, economy, society and culture, and even humanity itself. Excitement about AI comes about because it recognizes patterns and even discovers solutions that are superior to those based on human intelligence. The rapid progress of AI is greatly attributed to increased computing capabilities. In recent years, the computation power of integrated circuits (ICs) have been unable to sustain the growth rate according to Moore's law. Hardware accelerators, with processing units and optimized memory architecture designed specifically for parallel computing, played a key role in the implementation of machine learning (ML) models. However, electronic hardware accelerators have already been pushed to their limits in term of scalability, unable to keep up with the exponential growth of data volume. Against this backdrop, there have been renewed efforts in exploring the role of optics in computing, motivated by the large bandwidth and low loss of optical transmission. This project proposes the photonic tensor accelerator (PTA), a highly-parallel photonic architecture capable of matrix-vector multiplication and matrix-matrix multiplication, that offers a computing power several orders of magnitude higher than existing electronic accelerators. Thanks to its high degree of parallelization, PTA is specifically suited for batch matrix multiplication for the implementation of ANN models. The technology developed in this proposal could demonstrate the cooperative roles of advanced hardware and software and attract more students into hardware-related areas. The research proposed is interdisciplinary in nature and can serve as a platform for training both graduate and undergraduate students at UCF, a Hispanic Serving Institution (HSI) designated by the U.S. Department of Education.The overarching goal of this project is to construct photonic accelerators that 1) offer orders-of-magnitude higher scalability over electronics, 2) are fast, programmable, ideally compatible with training as well as inference, and 3) lower the power-consumption density to enable ANNs that are competitive over their pure electronic counterparts. The core of ANNs is tensor multiplication, which only require special operations (multiplication and accumulation, rather than general-purpose computing) in large scale that are especially suited for photonic accelerators. In addition, ANNs are robust to low dynamic range variabilities in nonlinear activation. PTA exploits all degrees of freedom of light to accelerate tensor multiplication. Specifically, PTA utilizes coherent beating between a signal and local oscillator to perform multiplication, frequency/wavelength, spatial modes and polarization for accumulation, and 2-D and 3-D parallelism of free space to scale the processing power. The proposed approach could scale the number of multiply-accumulate (MAC) operations by several orders of magnitude over the state-of-the-art IC hardware accelerators, including graphical processing units (GPUs) and ASICs such as tensor processing units (TPUs). The project will repurpose the technique of recirculating loops to scale up the number of layers for deep neural networks (DNNs). The proposed research is also synergistic with artificial intelligence (AI) in that some of the new devices will be designed using machine-learning techniques and the availability of the PTA-based ANNs allows new paradigms of ANN training.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.