FET: Small: Design Optimization of Silicon Photonic Integrated Circuits under Fabrication Process Variations

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Silicon photonics technology has made it possible to realize fully integrated photonic circuits with sub-micron silicon photonic devices. As a result, small and mobile photonic circuits can be developed that can perform a variety of optical functions for different applications, but with much lower cost and energy consumption. However, there is a fundamental issue that has limited the emergence of silicon photonic integrated circuits: the underlying silicon photonic devices in these circuits are extremely sensitive to fabrication-process variations. Indeed, nanometer-scale variations in the critical dimensions of silicon photonic devices considerably degrade the performance of the resulting circuits and even cause circuit failures. Unfortunately, the inability to efficiently characterize and compensate for fabrication-process variations have so far limited the development of cost-effective silicon photonic integrated circuits capable of delivering the true potential of silicon photonics. To combat this, the project involves research to realize energy-efficient and complex silicon photonic integrated circuits for different real-world applications that will be fully functional even in the presence of variation-plagued components. In addition, this project will create training opportunities for industrial participants and students at different levels to work on real-world problems while emphasizing the inclusion of underrepresented groups, thereby improving the education infrastructure and training highly skilled practitioners.The project contributions will involve developing: 1) comprehensive models of systematic and stochastic process variations in silicon photonics while incorporating both the probabilistic and non-probabilistic nature of uncertainties; 2) a framework to optimize silicon photonic sub-circuits and circuits under fabrication-process variations during design-time; and, and 3) energy-efficient circuit-level solutions to efficiently compensate for the impact of fabrication-process variations during run-time. For characterizing different variations, novel silicon photonic test structures and analytical algorithms will be designed to model different sources of fabrication-process variations and their impact. Efficient and compact stochastic analytical models will be developed to extensively explore and optimize silicon photonic sub-circuit and circuit performance under variations. For design-time optimization, the silicon-photonic integrated-circuit design problem will be modeled as a formal optimization problem to realize energy-efficient and robust circuits under fabrication-process variations. The performance under fabrication-process variations will be further improved by developing run-time self-correction mechanisms based on adaptive photonic signal multiplexing, robust signal routing and contention-management schemes, and dynamic adaptations for inexact circuit behavior under variations.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.