Collaborative Research: SHF: Small: Tangram: Scaling into the Exascale Era with Reconfigurable Aggregated "Virtual Chips"

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The design of general-purpose processors is reaching a performance bottleneck due to the limitations in technology scaling. Chiplet-based systems offer a promising solution by integrating small dies (chiplets) inside one package. Chiplets also enable heterogeneous integration of discrete chip architectures, such as CPUs, GPUs, DSPs, and FPGAs. However, the design of high-performance chiplet-based systems faces serious challenges: inter-chiplet communication is a critical bottleneck; resource needs to be efficiently shared among the chiplets to improve the performance-cost ratio; power and thermal management need to be optimized for better in-package integration. Consequently, such designs need to take a more holistic approach, and investigations are needed on the cross-cutting issues across the processing nodes, storage and interconnection fabric. This research proposes to build "virtual chips" from heterogeneous aggregated chiplets, so that the system can not only reap the performance benefit of a monolithic super chip but also break the scalability bottleneck. A major outcome of the project will be a set of optimization methods that enable the design of a reconfigurable architecture, leveraging a hybrid wireless interconnection to seamlessly connect the computing and memory components. To this end, the research goals include: (1) design of reconfigurable architectures to break the chiplet boundaries for efficient resource sharing; (2) development of models to quantify interactions between the applications and hardware resources for fast design-space exploration; (3) design of a hybrid wireless interconnection network to seamlessly bridge the physical gaps between chiplets and enable reconfigurable architectures through the flexibility of wireless networks; and (4) design of novel wireless antennas to improve energy and thermal efficiency.The proposed research bridges the gap between multiple layers of the design stack: hardware architectures, networks and devices. Due to its cross-cutting nature, the proposed research has the potential to transform the design of high-performance, energy-efficient and cost-effective systems that are able to meet the demand of emerging applications with growing bandwidth and performance needs. The educational contributions of this research include integrating research with teaching and training, design of tutorials and workshops focusing on the training of future engineers, and interaction with industry to accelerate technology transfer. Through the outreach activities as part of the proposed project, more undergraduate and minority students will be attracted to this field of engineering.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.