CCSS: Error-Correcting Codes Enabling Hyper-Speed Communications and Storage: from Theory to Hardware Architectures

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Hyper-speed communications and storage are required to access and utilize the exploding amount of data that is being generated, and are indispensable to the development of many paradigm-changing technologies, such as machine learning, Internet-of-things (IoT), and big data analytics. Driven by the needs of video streaming, social media, autonomous vehicles, etc., wireless data rate has been projected to reach 1Tb/s in 2030. Ubiquitous communications are incomplete without satellite links and optical backbones, which are following a similar data rate trend. Besides, high-speed satellite communications are essential to realizing fast connectivity in remote areas, enabling remote sensing for scientific recovery, and facilitating weather monitoring for disaster forecast. To cope with hyper-speed communications, computing, and analytics, the data access from storage devices also needs to reach commensurate speed. Although the feasibility of terabit/s front-end transceivers has been analyzed and storage class memories with very short sensing latency have been developed, the error-correcting codes (ECCs) that are needed to ensure data reliability have not been addressed for these systems. The requirement of hyper speed combined with the deteriorating communication and storage channels can not be tackled by extending existing ECC solutions. By nesting short sub-codewords, which allow very fast decoding with low complexity, to generate shareable parities, which improve the error-correcting capability by orders of magnitudes, the generalized integrated interleaved (GII) codes are the best candidate for next-generation terabit/s communications and storage.This project seeks to develop efficient hyper-speed and low-complexity GII decoder hardware implementation architectures for a broad range of applications. The nested decoding process of the GII codes faces many challenges, such as long data path that limits the achievable clock frequency, large silicon area, and low hardware utilization efficiency. Instead of directly translating the decoding algorithm to hardware implementations, in which case the achievable throughput is far below terabit/s and hardware complexity is high, integrated algorithmic reformulations and architectural optimizations will be exploited in this project. The mathematical computations leading to the hardware bottlenecks will be identified. Then those computations will be modified or eliminated by reformulating the algorithms without changing the decoding results. Such a cross-layer design approach allows unprecedented improvements on throughput, latency, and logic complexity. The silicon area and latency tradeoffs of various architectures for each decoding step will be evaluated, and a framework will be developed for GII decoder design to meet different system constraints under given code parameters and channel conditions. Besides, for the first time, GII decoders that are capable of handling soft probability information from the channel, such as by incorporating erasures and bit flips, will be investigated to further improve the error-correcting performance. New optimizations and reformulations will also be developed to efficiently implement the soft-decision decoders.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.