CCSS: Error-Correcting Codes Enabling Hyper-Speed Communications and Storage: from Theory to Hardware Architectures

超高速通信和存储是访问和利用正在生成的爆炸性数据量所必需的，并且对于许多改变范式的技术（如机器学习，物联网（IoT）和大数据分析）的开发是不可或缺的。在视频流、社交媒体、自动驾驶汽车等需求的推动下，无线数据速率预计将在2030年达到1 Tb/s。如果没有卫星链路和光纤主干网，无处不在的通信是不完整的，它们也遵循类似的数据速率趋势。此外，高速卫星通信对于实现偏远地区的快速连接、为科学恢复提供遥感以及为灾害预报提供气象监测都至关重要。为了科普超高速通信、计算和分析，存储设备的数据访问也需要达到相应的速度。虽然已经分析了太比特/秒前端收发器的可行性，并且已经开发了具有非常短的感测延迟的存储类存储器，但是确保数据可靠性所需的纠错码（ECC）还没有针对这些系统进行解决。超高速的要求与不断恶化的通信和存储通道相结合，无法通过扩展现有的ECC解决方案来解决。通过嵌套允许以低复杂度进行非常快速的解码的短子码字，以生成可共享的奇偶校验，这将纠错能力提高了几个数量级，广义综合交织（GII）码是下一代太比特/秒通信和存储的最佳候选码，本项目旨在开发高效的超高速和低比特率的GII码，复杂的GII解码器硬件实现架构，适用于广泛的应用。GII码的嵌套解码过程面临着许多挑战，例如长的数据路径限制了可实现的时钟频率，大的硅面积和低的硬件利用率。而不是直接翻译的解码算法的硬件实现，在这种情况下，可实现的吞吐量是远远低于太比特/秒和硬件复杂性高，集成的算法重新制定和架构优化将在这个项目中利用。将确定导致硬件瓶颈的数学计算。然后，在不改变解码结果的情况下，通过重新制定算法来修改或消除这些计算。这种跨层设计方法允许在吞吐量、延迟和逻辑复杂性方面实现前所未有的改进。将评估每个解码步骤的各种架构的硅面积和延迟权衡，并将为GII解码器设计开发一个框架，以满足给定代码参数和信道条件下的不同系统约束。此外，将首次研究能够处理来自信道的软概率信息（例如通过合并擦除和位翻转）的GII解码器，以进一步提高纠错性能。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Hyper-speed communications and storage are required to access and utilize the exploding amount of data that is being generated, and are indispensable to the development of many paradigm-changing technologies, such as machine learning, Internet-of-things (IoT), and big data analytics. Driven by the needs of video streaming, social media, autonomous vehicles, etc., wireless data rate has been projected to reach 1Tb/s in 2030. Ubiquitous communications are incomplete without satellite links and optical backbones, which are following a similar data rate trend. Besides, high-speed satellite communications are essential to realizing fast connectivity in remote areas, enabling remote sensing for scientific recovery, and facilitating weather monitoring for disaster forecast. To cope with hyper-speed communications, computing, and analytics, the data access from storage devices also needs to reach commensurate speed. Although the feasibility of terabit/s front-end transceivers has been analyzed and storage class memories with very short sensing latency have been developed, the error-correcting codes (ECCs) that are needed to ensure data reliability have not been addressed for these systems. The requirement of hyper speed combined with the deteriorating communication and storage channels can not be tackled by extending existing ECC solutions. By nesting short sub-codewords, which allow very fast decoding with low complexity, to generate shareable parities, which improve the error-correcting capability by orders of magnitudes, the generalized integrated interleaved (GII) codes are the best candidate for next-generation terabit/s communications and storage.This project seeks to develop efficient hyper-speed and low-complexity GII decoder hardware implementation architectures for a broad range of applications. The nested decoding process of the GII codes faces many challenges, such as long data path that limits the achievable clock frequency, large silicon area, and low hardware utilization efficiency. Instead of directly translating the decoding algorithm to hardware implementations, in which case the achievable throughput is far below terabit/s and hardware complexity is high, integrated algorithmic reformulations and architectural optimizations will be exploited in this project. The mathematical computations leading to the hardware bottlenecks will be identified. Then those computations will be modified or eliminated by reformulating the algorithms without changing the decoding results. Such a cross-layer design approach allows unprecedented improvements on throughput, latency, and logic complexity. The silicon area and latency tradeoffs of various architectures for each decoding step will be evaluated, and a framework will be developed for GII decoder design to meet different system constraints under given code parameters and channel conditions. Besides, for the first time, GII decoders that are capable of handling soft probability information from the channel, such as by incorporating erasures and bit flips, will be investigated to further improve the error-correcting performance. New optimizations and reformulations will also be developed to efficiently implement the soft-decision decoders.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.