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FET: Medium: Latch Ising Machines (LIM)

FET: Medium: Latch Ising Machines (LIM)
FET:介质:锁存机 (LIM)
批准号:
2106944
负责人:
Jaijeet Roychowdhury
金额:
$80.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2021
资助国家:
美国
项目状态:
未结题
起止时间:
2021-07-01 至 2025-06-30

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中文摘要
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英文摘要
Difficult computational (NP-complete) problems abound in today’s world, in areas as diverse as secure communications, protein folding, neural networks and healthcare. Large classes of these hard problems can be reduced to a form known as the Ising problem, which is closely related to the physics of ferromagnetic materials. The project team has devised a novel way of solving the Ising problem quickly and effectively in hardware, using networks of small, simple circuits, specifically, ``static'' memory cells, widely used in electronic devices of every kind. The concept significantly broadens the overall understanding of Ising machine schemes and their operational mechanisms. This project is developing this method (termed LIM) to practical fruition, including demonstration on real-world problems from communications. Being able to solve such real-world problems much more quickly and accurately than is currently practical can lead to broad benefits to society. The project's activities include a focus on students from traditionally disadvantaged backgrounds, as well as workshops for dissemination and interaction.More precisely, the team is showing that Ising machines, which have previously been realized using quantum/optical schemes as well as oscillator networks, can also be implemented using bi-stable elements such as CMOS-based latches. Unlike previous Ising machine approaches, which are large, expensive and ill-suited to low-cost mass production, the proposed approach is a purely classical scheme that does not rely on quantum phenomena or novel nano-devices. Using conventional CMOS electronics has many advantages: scalability/miniaturizability (i.e., very large numbers of spins in a physically small system), well-established design processes and tools that essentially guarantee first-time working hardware, very low power operation, seamless integration with control and I/O logic, easy programmability via standard interfaces like USB, and low cost mass production. Another key potential advantage stems from the continuous/analog nature of LIM (as contrasted with purely digital algorithms). The researchers are developing LIM theoretically and computationally, implementing it in hardware, and demonstrating it on benchmark Ising problems as well as Ising forms of difficult communications-related problems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(3)
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会议论文
Bistable Latch Ising Machines
双稳态锁存机
DOI: 10.1007/978-3-030-87993-8_9
发表时间: 2021
期刊: Proceedings
影响因子: --
作者: [Roychowdhury, Jaijeet]
通讯作者: Roychowdhury, Jaijeet
Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate Formulation
瞬态伴随 DAE 灵敏度:完整、严格且数值准确的公式
DOI: 10.1109/asp-dac52403.2022.9712537
发表时间: 2022
期刊: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC
影响因子: --
作者: [Sagan, Naomi, Roychowdhury, Jaijeet]
通讯作者: Roychowdhury, Jaijeet
A global Lyapunov function for the coherent Ising machine
相干伊辛机的全局李亚普诺夫函数
DOI: 10.1587/nolta.13.227
发表时间: 2022
期刊: IEICE
影响因子: --
作者: [Roychowdhury, Jaijeet]
通讯作者: Roychowdhury, Jaijeet
FET: Medium: ROCS: Recurrent Oscillatory Computing Systems for Rapid Solution of NP-Complete and Deep Learning Problems
  • 批准号:
    1901004
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $100.0万
  • 财政年份:
    2019
  • 负责人:
    Jaijeet Roychowdhury
  • 依托单位:
SHF: Medium: Booleanized Verification of Analog/Mixed Signal Systems
  • 批准号:
    1563812
  • 项目类别:
    Standard Grant
  • 资助金额:
    $90.0万
  • 财政年份:
    2016
  • 负责人:
    Jaijeet Roychowdhury
  • 依托单位:
SHF: Large: Phase-Based Logic Realized Using Oscillatory Nanosystems (PHLOGON)
  • 批准号:
    1111733
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $160.0万
  • 财政年份:
    2011
  • 负责人:
    Jaijeet Roychowdhury
  • 依托单位:
CAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Aggressor Blocks for Supply and Substrate Noise Analysis
  • 批准号:
    0541396
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $20.0万
  • 财政年份:
    2006
  • 负责人:
    Jaijeet Roychowdhury
  • 依托单位:
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