CAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Aggressor Blocks for Supply and Substrate Noise Analysis

点击翻译按钮获取中文摘要

ABSTRACT0541396Jaijeet RoychowdhuryU of Minnesota- Twin CitiesCAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Agressor Blocks for Supply and Substrate Noise AnalysisToday, virtually every aspect of our technological society today relies on a variety of digital and mixed-signal integrated circuits (ICs), which are growing larger and more complex by the day. To continue to design such chips effectively, estimating the interference noise generated by large numbers of switching digital blocks has become exceedingly important. Increasing levels of current drawn, higher switching speeds (clock frequencies) and falling supply voltages in new technologies conspire to worsen levels of interference noise and to exacerbate its debilitating impact on system functionality and performance. Interference noise that has not been correctly estimated and contained leads to failed production runs, delays in design turnaround,increased development costs and longer times to market. In this project, algorithms, methodologies and prototype CAD tools for predicting digital interference noise will be developed. The core of the project is to develop algorithms to extract accurate -- yet computationally-inexpensive -- noise macromodels of large blocks of digital aggressors. The resulting noisemacromodels will be used to develop a methodology for fast prediction of on-chip interference noise via both power-grid and substrate-coupling mechanisms. Unlike prior attempts, the project unified the prediction of interference noise digital design (e.g., switching noise margin, power/ground bounce induced delay variations) and for mixed-signal/analog/RF design (e.g., interference-induced spurs, SNR degradation and PLL jitter). Because the approach is algorithmically-based and not tied to any particular technology or design style, it is also easily adapted to apply nanoscale devices and mixed-domain systems containing electronics, optics, and MEMS. Thus, the project is expected to have significant broad impact in the general arena of high-performance hardware for communication, computational and sensor systems. The algorithms developed will be disseminated as open-source code, further accelerating and enhancing the project's impact in the technological community.