CAREER: Spintronic Devices Using Screw Dislocations in Single-Crystalline Semiconductors

该项目由电气、通信和网络系统(ECCS)部门的电子、光子学和磁性设备(EPMD)计划和既定的激励竞争研究计划(EPSCoR)共同资助。这一协同研究和教育计划旨在研究一种新型自旋场效应晶体管(自旋场效应晶体管)的器件物理，同时扩大聋人、西班牙裔和美洲原住民在纳米科学和工程方面的参与。这项工作将是第一次专注于利用单晶半导体中的螺位错的自旋场效应管的制造和表征的实验研究。螺位错是一种晶体缺陷，有望成为自旋晶体管在商业、工业和军事应用中在可变温度(即室温和更高温度)下工作的合适通道。该项目带来的知识和技术进步可能会加速高性能自旋电子器件的超大规模集成，这是实际实现混合和完全基于自旋的经典和量子计算机所必需的。该计划还将通过影响科学、技术、工程和数学(STEM)教育而造福社会。将建立针对K-12学生和公众的体验式展览，以扩大聋人、西班牙裔和美洲原住民在STEM中的参与。因此，这项工作将产生广泛的影响，向广泛的受众传播纳米科学、纳米技术和自旋电子学的价值，并有可能增加将在STEM工作的聋人、西班牙裔和美洲原住民的数量。研究工作包括三个高度重叠的智能线索：(I)自旋场效应晶体管的制备和结构表征嵌入螺旋位错(SDS)；(Ii)栅极可调自旋输运的表征；(Iii)在所制造的自旋场效应管中工艺-结构-性质关系的研究。所提出的自旋场效应管的工作原理是利用栅极电压来控制螺位错通道中的自旋寿命。两个相反排列的自旋选择铁磁/半导体接触将放置在螺位错的两端。由于位错芯中的自旋寿命预期较长，因此在此条件下晶体管将处于关断状态。在施加栅极电压的情况下，可以定制自旋极化以允许从一个铁磁触点到另一个铁磁触点的传输，从而使晶体管处于导通状态。自旋寿命和驰豫时间之间的比率将决定器件的开关比。以前已经提出了依赖于控制自旋寿命的自旋场效应管设计。然而，由于在室温下需要较大的(100ms)自旋弛豫时间，这些器件还没有得到实际应用。螺位错通道可以克服这一限制，这是由于一种独特的自旋-轨道耦合(SOC)形式，有望在高温下延长自旋寿命，从而使所提出的自旋场效应管设计能够实际应用。简而言之，Rashba和Dresselhaus SOC在中等离子物质的螺位错中的相互作用使自旋极化散射受到抵抗。该技术方案依赖于通过对超顺应性扭曲双晶体或先前已用受控扭曲角度覆盖的两个单晶纳米膜(NM)进行热处理来控制合成螺位错网络。NMS将提供比体相对应的更均匀的界面结合，扩展螺旋位错的半导体主机的调色板以包括外延生长的合金，并通过减少载流子的传输时间来提高晶体管的导通/关断比。错位的NMS将在自旋场效应管中进行处理，并将评估器件的工艺-结构特性关系。重点将放在碳化硅NMS中的SDS上，因为理论预测表明，在这种材料中可以获得固定的自旋取向，这种取向对所有形式的电子散射都是健壮的。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

“This project is jointly funded by the Electronics, Photonics, and Magnetic Devices (EPMD) Program of the Electrical, Communications and Cyber Systems (ECCS) Division, and the Established Program to Stimulate Competitive Research (EPSCoR)”. This synergistic research and education program aims to investigate the device physics of a novel spin field-effect transistor (spin FET) while broadening the participation of Deaf, Hispanics, and Native Americans in nanoscience and engineering. The work will be the first experimental study to focus on the fabrication and characterization of spin FETs that leverage screw dislocations in single srystal-crystalline semiconductors. A screw dislocation is a type of crystal defect that promises to act as a suitable channel for a spin transistor that operates at variable temperatures (i.e., room temperature and above) for commercial, industrial, and military applications. The improved knowledge and technological advances generated in this project will potentially accelerate very-large-scale integration of high-performance spintronic devices, which is required for the practical realization of hybrid and entirely spin-based classical and quantum computers. This program will also benefit society by impacting science, technology, engineering, and math (STEM) education. Experiential exhibits that will target K-12 students and the public will be established to broaden participation of Deaf, Hispanics, and Native Americans in STEM. As such, this work will have a wide-ranging impact by communicating the value of nanoscience, nanotechnology, and spintronics to a broad audience and potentially increasing the number of Deaf, Hispanics, and Native Americans that will pursue a career in STEM. The research effort encompasses three strongly overlapping intellectual threads: (i) fabrication and structural characterization of spin FETs embedded screw dislocations(SDs); (ii) characterization of gate-tunable spin transport; (iii) investigation of process-structure-property relationships in the fabricated spin FETs. The operation of the proposed spin FET is based on controlling the spin lifetime in screw dislocations channels using a gate voltage. Two opposite aligned spin-selective ferromagnetic/semiconductor contacts will be placed at the two ends of a screw dislocation. As the spin lifetime in the dislocation core is expected to be long, the transistor will be in an OFF state in this condition. Under an applied gate voltage, spin-polarization can be tailored to allow transport from one ferromagnetic contact to another, putting the transistor in an ON state. The ratio between the spin lifetime and the relaxation time will determine the ON/OFF ratio of the device. Spin FETs designs that rely on controlling spin lifetimes have been proposed before. However, these devices have not found practical uses due to the requirement of large (100 ms) spin relaxation times at room temperature. Screw dislocation channels can overcome this limitation owing to a unique form of spin-orbit coupling (SOC) that promises to increase spin lifetimes even at high temperatures, thereby enabling the practical application of the proposed spin FET design. Briefly, the interplay between Rashba and Dresselhaus SOC in screw dislocations of materials with medium ionicity makes spin polarization scattering resistant. The technical plan relies on the controlled synthesis of a screw dislocations network by annealing ultra-compliant twisted bicrystals or two single-crystalline nanomembranes (NMs) that have been previously overlayed with a controlled twist angle. NMs will provide more uniform interfacial bonding than their bulk counterpart, expand the palette of semiconductor hosts of screw dislocations to include epitaxially grown alloys, and increase the ON/OFF ratio of the transistor by reducing the transit time of the carriers. Dislocated NMs will be processed in spin FETs, and the process-structure property relationships of the devices will be evaluated. The focus will be on SDs in SiC NMs as theoretical predictions have shown that a fixed spin orientation, which is robust against all forms of electron scattering, can be obtained in this material.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.