CAREER: Advancing Combinatorial Optimization Accelerataors with Compute in Memory Design Approach

该奖项全部或部分由《2021年美国救援计划法案》（公法117-2）资助。组合优化问题存在于许多现实世界的社会和工业数据密集型计算应用中。例如，优化COVID-19疫苗的mRNA序列、半导体供应链和金融指数跟踪等。这类优化问题的计算量很大，随着问题规模的增加，寻找最优解的蛮力搜索方法就站不住脚了。解决优化问题的一种有效方法是通过将问题映射到伊辛模型上，让自然在物理世界中进行穷举搜索。Ising模型描述了铁磁体中的自旋动力学，其中自旋自然定向以达到最低能量状态，代表给定优化问题的最佳解。使用传统方法执行这样的Ising计算需要大量的计算迭代。这将导致频繁的片外存储器访问，并导致显著的能量开销。该项目的目标是推动节能和成本效益的组合优化硬件加速器的发展，以集成在现代集成电路中，以解决上述关键优化问题。本项目的研究成果将以课程设计案例研究的形式分发给学生。反过来，一些课程项目将与伊辛的加速器设计保持一致，从而实现紧密的研究与教学结合。该项目还旨在以本科生和研究生指导和研究经验的形式与代表性不足的少数民族学生接触。该项目提出了一种独特的模拟内存计算设计方法，通过重新配置现有的存储阵列电路来执行Ising计算。与先前的近内存、数字算术计算方法相比，这种内存计算方法在存储器阵列内的模拟域中以最小的电路变化执行伊辛哈密顿计算。它将哈密顿计算映射到可用的内存字线和位线电路上，这到目前为止仍然是一个关键的技术挑战。此外，该项目将研究跨多个存储库无缝映射大型Ising模型的方法，从而显着扩大Ising自旋计数。该项目旨在展示内存中计算的Ising加速器硅原型，进行设计空间探索，并量化与先前方法相比的优势。此外，该项目将利用大规模Ising模型探索未来复杂组合优化加速器的高密度内存需求。该项目将系统地研究新兴单片集成3D存储技术的器件技术电路协同设计方面。这可能会超越基于内存计算的Ising加速器在解决极端规模优化问题方面的优势。这项紧密结合的研究、教育和推广计划旨在建立密切的行业关系，将这项研究与研究生课程结合起来，提供在线课程，扩大K-12的推广，并在存储设备、电路设计和组合优化算法领域培训学生，以促进STEM劳动力的创造。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).Combinatorial optimization problems find many real-world social and industrial data intensive compute applications. Examples include optimization of mRNA sequences for COVID-19 vaccines, semiconductor supply-chains, and financial index tracking, to name a few. Such optimization problems are computationally intensive, and a brute-force search method for finding the optimum solution becomes untenable as the problem size increases. An efficient way to solve an optimization problem is to let nature perform the exhaustive search in the physical world by mapping the problem onto an Ising model. The Ising model describes spin dynamics in a ferromagnet, wherein spins naturally orient to achieve the lowest energy state, representing the optimal solution to a given optimization problem. Performing such Ising computations using conventional methods requires numerous compute iterations. This results in frequent off-chip memory accesses and incur significant energy overheads. The goal of this project is to advance the development of energy-efficient as well as cost-efficient combinatorial optimization hardware accelerators to be integrated in modern integrated circuits for solving critical optimization problems as mentioned above. The research results from this project will be disseminated to the students in the form of course design case-studies. Reciprocally, some of the course projects will be aligned with Ising accelerator designs enabling tight research-teaching integration. The project also aims to engage with underrepresented and minority students in the form of undergraduate and graduate student mentoring and research experiences. This project proposes a unique analog compute-within-memory design approach performing the Ising computations by reconfiguring existing memory array circuitry. In contrast to prior near-memory, digital-arithmetic computing approaches, this compute-in-memory approach performs Ising Hamiltonian computations in the analog domain within a memory array with minimal circuit changes. It maps Hamiltonian computations on to available memory wordline and bitline circuitry, which has remained a key technical challenge so far. In addition, this project will investigate the ways to seamlessly map large Ising models across multiple memory banks, thereby scaling up the Ising spin count significantly. The project aims to demonstrate compute-in-memory Ising accelerator silicon prototypes, perform design-space exploration, and quantify the benefits over prior approaches. Furthermore, the project will explore the high-density memory needs for future complex combinatorial-optimization accelerators utilizing large-scale Ising models. This project will systematically investigate device-technology circuit co-design aspects of emerging monolithically integrated 3D memory technologies. This can potentially leapfrog the benefits of compute-in-memory based Ising accelerators for solving extreme-scale optimization problems. The tightly-integrated research, education, and outreach plan aims to establish a close industry relationship, integrate this research with a graduate course, deliver online courses, expand K-12 outreach, and train students in the area of memory devices, circuit designs, and combinatorial-optimization algorithms in service of furthering the creation of the STEM workforce.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.