IRES Track 1: Impact of Emerging Information Processing Technologies on Architectures and Applications – a U.S.—French Partnership

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For over 30 years, MOS field effect transistors (MOSFETs) have been the mainstay of the now $400B/year semiconductor industry and are used to both process and store information “on chip.” The ability to continuously make transistors smaller (aka Moore's Law scaling) has fueled exponential improvements in computer processor size and performance. Unfortunately, transistor scaling has become limited by physics, cost, and manufacturing-related issues. Furthermore, constraints such as data center power budgets, the practical limits of air cooling, and the rise of mobile and edge connected devices in the internet of things (IoT) have all made energy efficiency an equally important design driver. IRES projects are motivated by (i) the semiconductor industry's search for devices/technologies to continue performance scaling trends historically associated with Moore's Law, and (ii) the need for new technologies and computer architectures to meet the computational needs of emerging application spaces at the edge. Researchers from the University of Notre Dame (ND) and mentors from Ecole Centrale de Lyon in France will work with Computer Science and Engineering (CSE) students from ND, as well as students from other institutions that are affiliated with ND led research centers, to study how new computer architectures that are enabled by emerging technologies will ultimately impact application-level drivers. A strong, diverse cohort of IRES researchers will be recruited via collaborations with leaders from the AnBryce Scholars Initiative, QuestBridge Scholars, STEM Scholars, and Posse programs. An overarching goal is to identify outstanding IRES candidates from minority, low-income, and first-generation student groups (as well as combinations thereof) from university departments whose academic focus would be in-line with that of this proposal. The Assistant Dean of Student Development (who oversees women in engineering and first-year engineering) will also be consulted to identify promising female students, as well as students from low income/first generation/other minority groups. In more technical detail, the coupling of technology, architecture, and applications is essential as the unique characteristics of new devices will lead to circuits and architectures that are fundamentally different from the existing state-of-the-art and may lead to new computational models for solving a given problem. Application-level analysis is the best – and frequently the only – way to judge the ultimate utility of a new device. A particular emphasis is placed on the impact of new technologies and models when applied to machine learning (via hardware support for algorithms that can learn with limited amounts of training data, as well as analog hardware to support efficient training/inference at the edge. Hardware architectures that merge logic and memory to support secure processing (e.g., AES and homomorphic encryption) are also considered. Systematic benchmarking of proposed hardware solutions against the state-of-the-art will also be done. This focus is well-suited for this IRES team given a US emphasis on technology driven hardware architectures, and a European focus on hardware solutions for the IoT. This project is funded by the Office of International Science and Engineering (OISE).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.