IRES Track 1: Impact of Emerging Information Processing Technologies on Architectures and Applications – a U.S.—French Partnership

30多年来，MOS场效应晶体管（MOSFET）一直是现在每年4000亿美元的半导体行业的支柱，用于处理和存储“芯片上”的信息。不断使晶体管变小的能力（又名摩尔定律缩放）推动了计算机处理器尺寸和性能的指数级改进。不幸的是，晶体管缩放已经受到物理、成本和制造相关问题的限制。此外，数据中心功率预算、空气冷却的实际限制以及物联网（IoT）中移动的和边缘连接设备的兴起等限制因素都使能源效率成为同等重要的设计驱动因素。IRES项目的动机是（i）半导体行业寻求设备/技术，以继续与摩尔定律相关的性能扩展趋势，以及（ii）需要新技术和计算机架构，以满足边缘新兴应用空间的计算需求。来自巴黎圣母院（ND）的研究人员和来自法国里昂中央理工学院的导师将与来自ND的计算机科学与工程（CSE）学生以及来自ND领导的研究中心附属的其他机构的学生合作，研究新兴技术支持的新计算机架构将如何最终影响应用级驱动程序。一个强大的，多样化的IRES研究人员队伍将通过与AnBryce学者倡议，QuestBridge学者，STEM学者和波塞计划的领导者合作招募。 一个总体目标是从少数民族，低收入和第一代学生群体（及其组合）中确定优秀的IRES候选人，这些学生来自大学部门，其学术重点与本提案一致。 还将咨询学生发展助理院长（负责监督工程和第一年工程中的妇女），以确定有前途的女学生以及来自低收入/第一代/其他少数群体的学生。在更多的技术细节中，技术，架构和应用程序的耦合是必不可少的，因为新设备的独特特性将导致电路和架构与现有的最先进的技术有根本的不同，并可能导致新的计算模型来解决给定的问题。应用程序级分析是判断新设备最终效用的最佳--通常也是唯一--方法。特别强调了新技术和模型在应用于机器学习时的影响（通过硬件支持可以使用有限数量的训练数据进行学习的算法，以及模拟硬件来支持边缘的有效训练/推理）。合并逻辑和存储器以支持安全处理的硬件体系结构（例如，AES和同态加密）也被考虑。还将根据最新技术水平对拟议的硬件解决方案进行系统的基准测试。这一重点非常适合这个IRES团队，因为美国强调技术驱动的硬件架构，而欧洲则专注于物联网的硬件解决方案。该项目由国际科学与工程办公室（OISE）资助。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

For over 30 years, MOS field effect transistors (MOSFETs) have been the mainstay of the now $400B/year semiconductor industry and are used to both process and store information “on chip.” The ability to continuously make transistors smaller (aka Moore's Law scaling) has fueled exponential improvements in computer processor size and performance. Unfortunately, transistor scaling has become limited by physics, cost, and manufacturing-related issues. Furthermore, constraints such as data center power budgets, the practical limits of air cooling, and the rise of mobile and edge connected devices in the internet of things (IoT) have all made energy efficiency an equally important design driver. IRES projects are motivated by (i) the semiconductor industry's search for devices/technologies to continue performance scaling trends historically associated with Moore's Law, and (ii) the need for new technologies and computer architectures to meet the computational needs of emerging application spaces at the edge. Researchers from the University of Notre Dame (ND) and mentors from Ecole Centrale de Lyon in France will work with Computer Science and Engineering (CSE) students from ND, as well as students from other institutions that are affiliated with ND led research centers, to study how new computer architectures that are enabled by emerging technologies will ultimately impact application-level drivers. A strong, diverse cohort of IRES researchers will be recruited via collaborations with leaders from the AnBryce Scholars Initiative, QuestBridge Scholars, STEM Scholars, and Posse programs. An overarching goal is to identify outstanding IRES candidates from minority, low-income, and first-generation student groups (as well as combinations thereof) from university departments whose academic focus would be in-line with that of this proposal. The Assistant Dean of Student Development (who oversees women in engineering and first-year engineering) will also be consulted to identify promising female students, as well as students from low income/first generation/other minority groups. In more technical detail, the coupling of technology, architecture, and applications is essential as the unique characteristics of new devices will lead to circuits and architectures that are fundamentally different from the existing state-of-the-art and may lead to new computational models for solving a given problem. Application-level analysis is the best – and frequently the only – way to judge the ultimate utility of a new device. A particular emphasis is placed on the impact of new technologies and models when applied to machine learning (via hardware support for algorithms that can learn with limited amounts of training data, as well as analog hardware to support efficient training/inference at the edge. Hardware architectures that merge logic and memory to support secure processing (e.g., AES and homomorphic encryption) are also considered. Systematic benchmarking of proposed hardware solutions against the state-of-the-art will also be done. This focus is well-suited for this IRES team given a US emphasis on technology driven hardware architectures, and a European focus on hardware solutions for the IoT. This project is funded by the Office of International Science and Engineering (OISE).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.