An Energy-Efficient, CMOS-based, and Scalable Mixed-Signal DNN System with Reconfigurable Crossbars

具有可重新配置交叉开关的节能、基于 CMOS 的可扩展混合信号 DNN 系统

• 批准号: 2221753
• 负责人: Mohammad Alhawari
• 金额: $ 41.89万
• 依托单位: Wayne State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-09-01 至 2025-08-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2221753&HistoricalAwards=false
• 关键词: Energy; Efficient; CMOS; based; Scalable

Deep neural networks have demonstrated high accuracy in a broad spectrum of applications, which are typically implemented on the cloud. However, it has become necessary to bring computation close to the data sources to address the data privacy, system latency, and energy consumption concerns, which are critical in applications such as healthcare, autonomous vehicles, and Internet-of-Things. Another arising issue relates to the typical use of digital systems to perform the necessary computations, but digital systems are fundamentally limited in handling big data efficiently. Although analog computation emerged as a promising alternative, which can outperform its digital counterpart by several orders of magnitudes in energy efficiency and computational speed, this alternative faces many challenges. First, emerging analog memories are unreliable, immature, and incompatible with standard CMOS technologies. Second, designing customizable and scalable analog deep neural networks that can support a broad range of deep neural networks is harder than the digital counterpart, leading to longer design cycles and higher costs. The broad goal of this project is to address these challenges by using innovative research directions in both analog and digital designs at the memory technology, circuit, architecture, and system levels, thereby enabling high scalability and great flexibility for various applications. This project will first develop a specialized electronic chip with a novel reconfigurable architecture and a new memory technology, utilizing a software-hardware co-design approach to achieve the necessary optimizations. Subsequently, this project will build a scalable system utilizing multiple such chips to adapt to the needs of even larger neural networks. This project will likely impact the design of future hardware accelerators because it improves energy efficiency, enhances computational speed, and enriches the functionality of deep neural networks while unlocking new capabilities of analog computations and allowing a massive deployment of edge devices. The educational aspects include filling the gap in the electrical and computer engineering curriculum related to deep neural network hardware implementation and providing various skills to participating students, focusing on minority and underrepresented groups. The extensive outreach activities include developing and teaching two summer project-oriented courses in machine learning and circuit design for K-12 students in metro Detroit. This project proposes multiple innovations at the technology, circuit, architecture, and system levels. At the memory technology level, we propose a new, CMOS-based, analog multi-stable memory circuit that offers compatibility with crossbar systems, provides an analog solution to store the weights, and performs local computations in a highly parallel and energy-efficient manner. At the circuit level, we propose a local storage and processing unit, which employs the proposed analog memory to perform multiply-and-accumulate operations, utilizing only one memory unit to support both positive and negative weights. At the architecture level, we propose a novel reconfigurable architecture to construct a scalable and highly customizable inference engine. In this architecture, crossbar cells can be expanded horizontally and/or vertically using switch matrix circuits, thereby improving the utilization and reducing the power consumption compared to the fixed-size and separate crossbar arrays. Moreover, we propose the usage of a pool of reconfigurable digital-to-analog converters and analog-to-digital converters, which are well suited for the reconfigurable architecture, and will optimize their bit resolutions for each deep neural network layer. Furthermore, the proposed inference engine employs a low-power open-source processor (specifically RISC-V) to enable high flexibility and provide various functions, including the management of the data flow between layers, configuration, and calibration. To minimize the fetch/decode energy consumption, custom digital circuits will be developed to support non-linear and pooling functions. To account for process variations, we will exploit built-in-self-test and built-in-self-calibration techniques to test and calibrate all the analog circuits, utilizing on-chip circuits and configuration registers. Finally, at the system level, multiple chips will be interconnected through PCI Express to support larger models.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

深度神经网络在广泛的应用中表现出很高的精度，这些应用通常在云上实现。但是，已经有必要将计算靠近数据源来解决数据隐私，系统延迟和能源消耗问题，这些问题在医疗保健，自动驾驶汽车和图像等应用中至关重要。另一个出现的问题涉及数字系统执行必要计算的典型使用，但是在有效地处理大数据方面，数字系统在根本上受到限制。尽管模拟计算是一种有希望的替代方案，它可以通过能源效率和计算速度的几个数字来胜过其数字对应，但这种替代方案面临许多挑战。首先，新兴的模拟记忆不可靠，不成熟，并且与标准CMOS技术不兼容。其次，设计可自定义和可扩展的模拟深度神经网络可以支持广泛的深神经网络比数字对应物更难，从而导致更长的设计周期和更高的成本。该项目的广泛目标是通过在内存技术，电路，体系结构和系统级别上使用创新的研究方向来应对这些挑战，从而为各种应用提供高可扩展性和极大的灵活性。该项目将首先开发一种具有新颖的可重构体系结构和新的内存技术的专业电子芯片，并利用软件硬件共同设计方法来实现必要的优化。随后，该项目将利用多个此类芯片来构建一个可扩展系统，以适应更大的神经网络的需求。该项目可能会影响未来硬件加速器的设计，因为它可以提高能源效率，提高计算速度并丰富深层神经网络的功能，同时解锁模拟计算的新功能并允许大量部署边缘设备。教育方面包括填补与深度神经网络硬件实施相关的电气和计算机工程课程的空白，并为参与的学生提供各种技能，重点关注少数群体和代表性不足的群体。广泛的外展活动包括在底特律地铁的K-12学生中开发和教两种面向夏季的机器学习和电路设计课程。 该项目提出了技术，电路，体系结构和系统级别的多次创新。在存储技术级别上，我们提出了一种基于CMO的新的，模拟的多稳定内存电路，该记忆电路可与横梁系统兼容，提供了一种模拟解决方案来存储权重，并以高度平行和能效的方式执行本地计算。在电路级别，我们提出了一个本地存储和处理单元，该存储和处理单元采用了建议的模拟内存来执行多重和蓄积的操作，仅利用一个内存单元来支持正权重。在体系结构层面，我们提出了一种新颖的可重构体系结构，以构建可扩展且高度可定制的推理引擎。在此体系结构中，可以使用开关矩阵电路水平扩展横梁单元格，从而改善利用率并减少与固定大小和独立的横杆阵列相比的功耗。此外，我们建议使用可重新配置的数字到分析转换器和模数转换器的使用池，这些转换器非常适合可重构体系结构，并将优化其对每个深神经网络层的位分辨率。此外，所提出的推理引擎采用低功率开源处理器（特别是RISC-V）来实现高灵活性并提供各种功能，包括对图层，配置和校准之间的数据流进行管理。为了最大程度地减少获取/解码能源消耗，将开发自定义数字电路以支持非线性和汇总功能。为了说明过程变化，我们将利用芯片电路和配置寄存器来利用内置测试和内置校准技术来测试和校准所有模拟电路。最后，在系统级别上，将通过PCI Express进行多个芯片，以支持更大的模型。该奖项反映了NSF的法定任务，并被认为是值得通过基金会的知识分子优点和更广泛的影响评估标准通过评估来支持的。

项目成果

Analysis of Dual-Row and Dual-Array Crossbars in Mixed Signal Deep Neural Networks

混合信号深度神经网络中双行双阵列交叉开关的分析

• 发表时间: 2023
• 期刊: IEEE international Midwest Symposium on Circuits and Systems
• 作者: Edwards, Melvin D.;Sarhan, Nabil J.;Alhawari, Mohammad
• 通讯作者: Alhawari, Mohammad