SHF: EAGER: Toward Energy-Efficient Heterogeneous Computing Integrating Polymorphic Magnetic and CMOS Devices

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The integration of non-conventional materials and devices with silicon Complementary Metal Oxide Semiconductor (CMOS) technology can enable a new type of computing platform with potential benefits related to area, energy efficiency, and resiliency. In this regard, storing and manipulating information in magnetic devices is promising. This is because, unlike CMOS devices, information in magnetic devices can be stored without any energy dissipation, while energy is needed only to read or write information. This low-power operation of magnetic devices is highly advantageous for applications such as Internet of Things and intelligent sensing that have low operating power requirements. This research will connect the physics of such magnetic devices with their use in circuits in which magnetic devices co-exist with and complement silicon devices for enhanced functionality and user experience. Results from this research will be incorporated into a hands-on circuit design workshop organized annually at New York University (NYU). Specifically, students will learn about the physics of magnets in table top experiments and interactive online learning tools. The project will also develop content on magnetic memory that will be introduced in a course on nanoelectronics devices and circuits taught annually at NYU. The project will also publicly release the device models and simulation data generated in this research via the science and engineering gateway hosted at Purdue University, known as the nanoHUB, to benefit researchers and educators working in related fields.While other possibilities exist, this particular project will focus on two specific magnetic devices, namely the voltage-controlled topological-spin switch (vTOPSS) and the magneto-electric spin-orbit (MESO) device. These magnetic devices offer 10 to 100 times superior energy efficiency for binary operations compared to their magnetic counterparts. Another unique feature of these devices is that their logic functionality can be configured post-fabrication, which translates into resilience and area- and power benefits at the circuit and system level. Physics-based models of the latency, energy dissipation, thermal stability, and error-rate of vTOPSS and MESO device will be developed and calibrated against large-scale Monte-Carlo simulations. Impact of potential interconnects, including metallic and semiconducting nanowires, on device performance will be quantified. Device-level models will be used to develop a standard cell library of Boolean logic gates with vTOPSS and MESO as the switching elements. The cell library will enable the quantification of performance metrics of magnetic-CMOS computing platform at scale. The physics-to-circuits approach adopted in this research will drive innovative concepts in circuit design that can maximize the competitiveness of the proposed technology.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.