CAREER: Near-Memory Datacenter Network

点击翻译按钮获取中文摘要

Datacenters are the backbone of today’s digital world that power all daily cloud services. Over the past decade, the exponential increase in the data volumes resulted in computing specialization and over a 100x increase in datacenter network bandwidth utilization. Nevertheless, the network data delivery path to the compute nodes remained unchanged. As such, the current datacenter network suffers from the overhead of the multi-layered software stack, complex network protocol processing, frequent data movement, and network device management. The project novelty is to leverage hardware specialization and near-data processing to re-architect a datacenter’s network. The project's educational plans include organizing yearly outreach workshops to educate K-12 teachers on computing fundamentals, involving underrepresented, undergraduate, and low-income students in research, and integrating research into the higher-education curriculum. Such activities boost student enrollment in higher-educational institutions, train diverse students who deeply understand computer architecture and systems fundamentals, and can innovate across architecture, networking, and operating systems fields. The project’s impacts are to shape the future of datacenter networking and educate a high-quality workforce to supply the needs of the US IT industry and academia.The project aims to design, implement, and evaluate a network data plane that delivers data directly from top-of-rack switch ports to the server’s Central Processing Unit (CPU) caches and memory modules, leveraging an optical interconnection network. The investigator extends the CPU Instruction Set Architecture (ISA) with several network access instructions that enable a process to access the network with minimal software activity. The memory access instructions offload the notification between the CPU and the network interfaces to the hardware. The investigator develops libraries and transport protocols that utilize the proposed network data and control plane to provide robust connectivity between processes running on different servers. Lastly, the project explores the design space of domain-specific near-memory accelerators for network protocol acceleration. The potentially transformative network architecture will enable compute nodes to efficiently sustain tera-bit-per-second connectivity with bare metal network latency numbers. The investigator uses the research findings and evaluation infrastructure to boost the home institution's computer architecture and systems pedagogy.This project is jointly funded by the Software and Hardware Foundations (SHF) core research program in the Computing and Communication Foundations (CCF) Division and the Established Program to Stimulate Competitive Research (EPSCoR).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.