ERI: FD-WiNoC: Area and Energy Efficient Full Duplex Transceiver System for Wireless Network on Chip

同时同频全双工无线通信缓解了现有同时半双工通信中带宽利用率低的问题。在全双工模式下，信号的发送和接收在同一频带内同时进行。设计这种全双工无线设备的主要挑战是自干扰。在收发器中本地产生并因此具有非常高功率电平的发射信号干扰同一频段内的低功率接收信号。因此，接收到的信号被淹没在来自本地发射机的“自干扰噪声”中，无法恢复。在过去的十年中，已经提出了几种技术来减少自干扰信号到可以忽略的水平，从而消除自干扰。目前的项目目标是将自干扰消除到60 dB或更高，这足以满足芯片上无线网络（WiNoCs）等片上无线通信。自干扰消除对WiNOCs尤其重要，因为WiNOCs需要高数据速率（10gbps或更高）来支持当今高性能多核计算机体系结构，这需要同时双向数据传输来支持实时应用。全双工架构将消除传输和接收两组独立频带的需求，从而将多个亚太赫兹频带的需求减少一半。这有助于减轻CMOS技术的严重设计挑战。这项研究的成功将激发在60 GHz和次太赫兹频率下使用先进的亚20纳米射频FinFET技术的系统级研究，以评估所提出的新型WiNoC架构的性能，并将其与其他现有架构进行比较。此外，WiNoC应用的全双工收发器系统的验证将扩展对其他片上通信（如小芯片之间的无线互连或无线神经加速器架构）的全双工能力的研究见解。该项目为学生提供培训机会，包括来自STEM中代表性不足的少数群体的学生，以学习半导体集成电路设计技术，为未来在半导体行业的职业生涯做好准备。该项目旨在开发一种新型的同时同频全双工收发器系统，用于具有成本效益的射频CMOS技术的无线片上网络（WiNoC）应用。这项工作是建立在初步可行性研究的基础上，并将通过以下研究任务进行基础研究，以提高WiNoC应用的全双工收发电路的性能：a)设计一种新型的能量和面积效率高的发射机电路，内置模拟对消，工作频率为5 GHz，采用成本效益高的110纳米射频CMOS技术中的开关键控（OOK）或其他非相干调制，将自干扰对消提高到40 dB或更高；b)设计一种相同频率的接收器前端电路，采用相同的技术，采用新型的高性能无电感低噪声放大器（LNA），以提高面积效率。c)在上述设计的基础上，利用模拟对消电路在模拟域进行自干扰对消，并开发频谱估计或其他类似技术，实现对残余信号的高数字对消，将总自干扰对消提高到60 dB或更高，以满足WiNoC的实际应用；D)设计同时同频全双工收发器系统的原型，通过实验测量验证所有性能参数，作为概念验证。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The co-time co-frequency full-duplex wireless communication alleviates the issue of inefficient use of bandwidth in the existing co-time half-duplex communication. In the full-duplex mode, the transmission and reception of signals take place simultaneously in the same frequency band. The primary challenge in designing such a full-duplex wireless device is self-interference. The transmit signal which is locally generated in the transceiver and thus has a very high power level interferes with the low power received signal in the same frequency band. The received signal is thus submerged in the ‘self-interfered noise’ from the local transmitter and cannot be recovered. Several techniques have been suggested over the last decade to reduce the self-interference signal to the level where it can be neglected, thus eliminating self-interference. The current project targets to bring the self-interference cancellation to 60 dB or more, which is sufficient for on-chip wireless communications such as wireless network on chips (WiNoCs). The self-interference cancellation is particularly important for WiNOCs because WiNoCs will need high data rates (10 Gbps and beyond) to support today’s high performance multi-core computer architecture which require simultaneously bidirectional data transfer to support real-time applications. A full-duplex architecture will eliminate the need of two separate sets of frequency bands for transmission and reception, and hence reduce the demand of multiple sub-THz frequency bands by half. This help mitigate serious design challenges with CMOS technologies. The success of this research will motivate system-level study with advanced sub-20-nm RF FinFET technologies at 60 GHz and sub-THz frequencies to evaluate the performance of the proposed novel WiNoC architecture and compare it with other existing architectures. Furthermore, the validation of the full-duplex transceiver system for WiNoC applications will expand research insights for full-duplex capability of other on-chip communications such as wireless interconnects between chiplets or a wireless neural accelerator architecture. The project provides training opportunities for students, including those from underrepresented minority groups in STEM, to learn semiconductor integrated circuit design techniques and prepare themselves for future career in semiconductor industry. The project aims to develop a novel co-time co-frequency full-duplex transceiver system for wireless network on chip (WiNoC) applications in a cost-effective RF CMOS technology. The work is built on a preliminary feasibility study and will conduct fundamental research to improve the performance of the full-duplex transceiver circuit for WiNoC applications by the following research tasks: a) designing a novel energy- and area-efficient transmitter circuit with built-in analog cancellation, operating at 5 GHz and using the On-Off Keying (OOK) or other non-coherence modulation in a cost-effective 110-nm RF CMOS technology, to improve the self-interference cancellation to 40 dB or higher, b) designing a receiver front-end circuit at the same frequency and using the same technology with a novel high performance inductor-less low noise amplifier (LNA) for area efficiency, c) augmenting the above designs with self-interference cancellation in analog domain with the analog cancellation circuit and developing spectral estimation or other similar techniques to achieve a high digital cancellation of the residual signal to enhance the total self-interference cancellation to 60 dB or higher for practical applications of WiNoC, d) designing a prototype of the co-time co-frequency full-duplex transceiver system to validate all the performance parameters with experimental measurements as a proof of concept.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.