ERI: FD-WiNoC: Area and Energy Efficient Full Duplex Transceiver System for Wireless Network on Chip

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The co-time co-frequency full-duplex wireless communication alleviates the issue of inefficient use of bandwidth in the existing co-time half-duplex communication. In the full-duplex mode, the transmission and reception of signals take place simultaneously in the same frequency band. The primary challenge in designing such a full-duplex wireless device is self-interference. The transmit signal which is locally generated in the transceiver and thus has a very high power level interferes with the low power received signal in the same frequency band. The received signal is thus submerged in the ‘self-interfered noise’ from the local transmitter and cannot be recovered. Several techniques have been suggested over the last decade to reduce the self-interference signal to the level where it can be neglected, thus eliminating self-interference. The current project targets to bring the self-interference cancellation to 60 dB or more, which is sufficient for on-chip wireless communications such as wireless network on chips (WiNoCs). The self-interference cancellation is particularly important for WiNOCs because WiNoCs will need high data rates (10 Gbps and beyond) to support today’s high performance multi-core computer architecture which require simultaneously bidirectional data transfer to support real-time applications. A full-duplex architecture will eliminate the need of two separate sets of frequency bands for transmission and reception, and hence reduce the demand of multiple sub-THz frequency bands by half. This help mitigate serious design challenges with CMOS technologies. The success of this research will motivate system-level study with advanced sub-20-nm RF FinFET technologies at 60 GHz and sub-THz frequencies to evaluate the performance of the proposed novel WiNoC architecture and compare it with other existing architectures. Furthermore, the validation of the full-duplex transceiver system for WiNoC applications will expand research insights for full-duplex capability of other on-chip communications such as wireless interconnects between chiplets or a wireless neural accelerator architecture. The project provides training opportunities for students, including those from underrepresented minority groups in STEM, to learn semiconductor integrated circuit design techniques and prepare themselves for future career in semiconductor industry. The project aims to develop a novel co-time co-frequency full-duplex transceiver system for wireless network on chip (WiNoC) applications in a cost-effective RF CMOS technology. The work is built on a preliminary feasibility study and will conduct fundamental research to improve the performance of the full-duplex transceiver circuit for WiNoC applications by the following research tasks: a) designing a novel energy- and area-efficient transmitter circuit with built-in analog cancellation, operating at 5 GHz and using the On-Off Keying (OOK) or other non-coherence modulation in a cost-effective 110-nm RF CMOS technology, to improve the self-interference cancellation to 40 dB or higher, b) designing a receiver front-end circuit at the same frequency and using the same technology with a novel high performance inductor-less low noise amplifier (LNA) for area efficiency, c) augmenting the above designs with self-interference cancellation in analog domain with the analog cancellation circuit and developing spectral estimation or other similar techniques to achieve a high digital cancellation of the residual signal to enhance the total self-interference cancellation to 60 dB or higher for practical applications of WiNoC, d) designing a prototype of the co-time co-frequency full-duplex transceiver system to validate all the performance parameters with experimental measurements as a proof of concept.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.