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NSF ACED: ROOTS: Real-time Optimization Of Transceiver Systems

NSF ACED: ROOTS: Real-time Optimization Of Transceiver Systems
NSF ACED:ROOTS:收发器系统的实时优化
批准号:
2314813
负责人:
Jeffrey Walling
金额:
$50.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2023
资助国家:
美国
项目状态:
未结题
起止时间:
2023-07-01 至 2026-06-30
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中文摘要
翻译
未来的无线系统,例如为第六代无线网络(6G)提出的那些系统,将在我们现有的网络能力的基础上扩展,并提供新的和新兴的服务,如增强/虚拟现实、远程手术、传感和环境成像。这将需要比前几代无线网络所需的更精确的新无线电路和系统。这项研究的目标是利用机器学习不断提高无线电路和系统的精确度和准确度。这可以使无线设备更高效地运行,并提供更强大的无线连接。拟议的调查还将为将机器学习直接嵌入射频收发机硬件提供洞察力。这项以芯片研究为重点的研究将导致新的集成电路和集成技术的设计,这些集成电路和集成技术在6G中具有广阔的应用前景。除了调查的科学结果,这项提案还涉及美国和台湾大学之间的国际合作。教育目标将在两国合作的大学之间交叉培养4名博士和4名硕士学生。调查人员还计划为电路和系统设计的本科生和研究生课程开发课程,并计划让教育发展早期课程的本科生参与与提案相关的研究。这项提案的目的是调查使用机器学习来持续校准和优化毫米波(毫米波)收发机硬件。这是有必要的,因为6G的预测扩大了毫米波和近太赫兹频谱的使用,这要求电路和系统能够灵活操作,并在更宽的瞬时带宽上具有更好的线性度。商业化生产的收发器现在使用100s-1000s的比特进行微调和校准;然而,其中许多微调仅在自动测试设备上对集成电路进行初始编程时执行。这创造了一个很大的校准和优化空间,这个项目将使用一个局部的、高效的神经形态记忆计算系统来研究连续的背景优化。作为该计划的一部分,高度可调整的数字发射机将与一个低功率校准接收器集成在一起,该接收器将用于估计发射机参数。接收器的输出将被输入到带有内存计算(CIM)的神经形态计算加速器中,该加速器将运行校准/优化算法,控制发射器修剪和校准比特。该项目分为两个阶段。在第一阶段,收发电路和神经形态计算加速器将分别设计和表征。它们将被联合打包,用于系统之间接口的初步调查。在第二阶段,第一阶段的实验结果将被用来指导第二阶段的整合。第二阶段演示实验包括一个完全集成的系统和系统优化实验,以提高系统的效率和线性度。这些实验的结果将为未来增加复杂性的系统的规模设计提供相关信息,包括用于无线波束形成的多输入、多输出系统。该奖项反映了NSF的法定使命,并通过使用基金会的智力优势和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Future wireless systems such as those proposed for the sixth generation of wireless networks (6G) will expand upon our present networking capability and provide for new and emerging services such as augmented/virtual reality, remote surgery, sensing, and imaging of our environment. This will require new wireless circuits and systems that are more precise than those required for previous generations of wireless networks. The goal of this research is to use machine learning to continuously improve the precision and accuracy of wireless circuits and systems. This can enable wireless devices to operate more efficiently and provide more robust wireless connectivity. The proposed investigation will also provide insight into embedding machine learning directly with RF transceiver hardware. This research that is focused on the investigation of CHIPS will result in the design of novel integrated circuit and integration techniques that are promising for 6G. In addition to the scientific outcomes of the investigation, this proposal involves international collaboration between universities in the United States and Taiwan. The educational objectives will cross-train 4 Ph. D. and 4 M.S. students between the partnering universities in both countries. The investigators also plan curriculum development for their undergraduate and graduate courses in circuits and systems design and plan to involve undergraduate students from their courses at earlier stages of their educational development in the research associated with the proposal.The objective of this proposal is to investigate the use of machine learning to continuously calibrate and optimize millimeter wave (mmWave) transceiver hardware. This is warranted because the projections for 6G expand the use of mmWave and near-THz spectrum, which require circuits and systems that can operate flexibly and with better linearity across wider instantaneous bandwidth. Commercially produced transceivers now use 100s-1000s of bits for trimming and calibration; however, many of these trims are only performed at the initial programming of the integrated circuit on automated testing equipment. This creates a large calibration and optimization space that this project will use to investigate continuous background optimizations using a local, efficient neuromorphic compute-in-memory system. As part of the program, highly trimmable digital transmitters will be integrated with a low-power calibration receiver that will be used to estimate transmitter parameters. The outputs of the receiver will be input into a neuromorphic computing accelerator with compute-in-memory (CIM) that will be running calibration/optimization algorithms that control the transmitters trimming and calibration bits. The project has two phases. In the first phase, the transceiver circuits and neuromorphic computing accelerator will be designed separately and characterized. They will be co-packaged for initial investigation of the interface between the systems. In the second phase, the experimental findings from phase one will be used to guide integration in phase two. The phase two demonstration experiment includes a fully integrated system and experiments on system optimizations to improve the system efficiency and linearity. The findings from these experiments will provide relevant information to scale designs for future systems that add complexity including multiple-input, multiple-output systems for wireless beamforming.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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CCSS: Switched Capacitor Power Amplifiers for Digital MIMO Transmitters
  • 批准号:
    1508701
  • 项目类别:
    Standard Grant
  • 资助金额:
    $22.68万
  • 财政年份:
    2015
  • 负责人:
    Jeffrey Walling
  • 依托单位:
海外基金