Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications

合作研究：CMOS X：用于新兴计算应用的 CMOS 上大规模集成 FeFET 的设备到架构联合开发和演示

• 批准号: 2318808
• 负责人: Kai Ni
• 金额: $ 24万
• 依托单位: Rochester Institute of Tech
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-09-01 至 2024-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2318808&HistoricalAwards=false
• 关键词: Collaborative; Research; CMOS+X; Device; Architecture

In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, AR/VR, autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As CMOS technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, HfO2 based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在人工智能的新时代，现代计算电子面临着巨大的挑战，大量的计算任务，如机器人，AR/VR，自动驾驶，需要巨大的计算模型和巨大的计算工作量的支持。 这种需求使现有电子硬件的能力相形见绌。 随着CMOS技术接近1 nm节点，很明显，传统的技术缩放将很快失去动力，以满足不断增长的计算能力需求。 为了延续摩尔定律，基于HfO 2的铁电场效应晶体管（FeFET）是具有组合的非易失性、高能量效率和与CMOS兼容的优点的主要候选者之一。 虽然已经在FeFET上进行了许多器件级开发，但其中一个阻碍因素是器件的开发通常在小规模下进行，而没有与CMOS技术的高水平集成，这对于提供用于支持现代计算任务的完整集成电路（IC）解决方案是必要的。 为了克服现有发展的局限性，该提案将开发从器件到电路和架构的跨层技术，使具有高度前景的FeFET器件与标准CMOS技术实现大规模集成。该项目将执行从器件到架构的全栈开发，以集成CMOS和FeFET技术，目标是新兴的计算应用。在先进的技术节点，在大规模的CMOS制造FeFET将被用来证明所提出的技术。更具体地说，我们将执行以下开发。 在器件层面，将开发nFeFET、pFeFET和CMOS之间集成的改进工艺，使FeFET和CMOS器件实现更好的技术融合;在设计方法学方面，将开发联合器件-电路协同设计流程，以定制FeFET技术满足人工智能等新兴计算应用的需求;此外，将开发利用FeFET作为存储器和计算设备的新型电路和架构，以利用FeFET的特性及其与CMOS技术的共存;最后，还将展示针对新兴应用的复杂处理器和加速器，以及CMOS和FeFET联合技术，以展示集成CMOS的新兴器件的优势。 CMOS和FeFET融合的集成方法和演示将体现FeFET器件的系统前景，并为未来FeFET的发展，特别是新兴的计算任务奠定坚实的基础。 透过将先进的半导体技术与新兴的计算任务相结合，拟议的项目为学生提供了强大的教育材料和机会，让他们了解现代计算技术和微电子器件的多学科发展。 该奖项旨在为社会提供坚实的培训，同时促进大学STEM教育的多样性和包容性。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。