Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications

协作研究：SHF：Medium：内存计算结构跨层基准测试的综合建模框架：从设备到应用程序

• 批准号: 2212240
• 负责人: Kai Ni
• 金额: $ 42.82万
• 依托单位: Rochester Institute of Tech
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-09-01 至 2023-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2212240&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Comprehensive

This project will develop a framework for rapid and accurate design-space explorations of application-level workloads assuming technology-enabled in-memory computing (IMC), which is at present being investigated for a range of application spaces (AI/machine learning, bioinformatics, graph processing, etc.). IMC is of great interest as more and more compute workloads must process ever growing amounts of data. Frequently, the energy and latency associated with data transfer from a computer’s memory to a processor can overwhelm the cost of the processing itself. As such, it is highly desirable to co-locate processing and memory. Work in the project will result a publicly available, curated framework that leverages both existing device models and design tools, and that incorporates new device models and design tools to properly evaluate the IMC design space with at-scale, application-level workloads. A modeling and evaluation infrastructure will be developed to address the above design/evaluation challenges as there is an obvious need to explore a vast design space. Investigators in this project will also work with K-8 teachers to augment existing STEM curricula with material that exposes students to fundamental concepts and skills in computer science. This is especially relevant as computer science concepts are now assessed on state-wide standardized tests. Students from under-represented groups will be recruited and mentored via REU experiences.To explore the IMC design space, device-level modeling, circuit/architectural-level modeling, device non-ideality (e.g., variation) analysis, and ways to integrate heterogeneous architectural solutions that target specific application-level workloads must all be studied. In the IMC space, (i) the number of candidate technologies is large and ever-changing, (ii) multiple candidate IMC circuits and architectures – e.g., computing at the array periphery (CAP), content addressable memories (CAMs) and crossbars – exist, (iii) IMC solutions may be more susceptible to device variations/non-idealities, and this impact must be captured at the application level, (iv) emerging technology-enabled IMC solutions may be used with existing architectural solutions and/or in a variety of heterogenous designs, and (v) there are effectively an infinite number of application-level mappings/potential algorithmic changes that one might consider. With respect to device models, there is a deliberate focus on ferroelectric devices – i.e., front-end-of-line silicon ferroelectric field effect transistors, back-end-of-line metal-oxide ferroelectric field effect transistors, and multi-gate ferroelectric field effect transistors – owing to ever-growing interest in this technology as well as the need to consider monolithic 3D processing/memory systems. For IMC circuits/architectures, this project will expand and develop modeling/evaluation tools for two different “flavors” of computing in memory – (i) CAMs (that can report memory entries that best match a given query) and (ii) CAP. For CAMs, representative efforts include projecting figures of merit for binary, ternary, multi-level, and analog CAM arrays (read/write energy and latency, etc.) designs implemented with different non-volatile memories, for different matching functions. Determining optimal CAM array sizes and other design parameters will also be considered. Evaluation of CAP designs for different NVMs will also be developed. For applications, solutions based on IMC fabrics for a subset of applications from MLPerf will be evaluated. MLPerf represents a consortium of AI leaders who have derived relevant workloads for vision, language, etc.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

该项目将开发一个框架，用于快速准确地设计应用级工作负载的空间探索，假设技术支持的内存计算（IMC），目前正在研究一系列应用空间（AI/机器学习，生物信息学，图形处理等）。 IMC非常有趣，因为越来越多的计算工作负载必须处理不断增长的数据量。通常，与从计算机的存储器到处理器的数据传输相关联的能量和延迟可以压倒处理本身的成本。 因此，高度期望将处理和存储器共同定位。该项目的工作将产生一个公开可用的策划框架，该框架利用现有的设备模型和设计工具，并结合新的设备模型和设计工具，以正确评估具有大规模应用级工作负载的IMC设计空间。将开发建模和评估基础设施，以解决上述设计/评估挑战，因为显然需要探索广阔的设计空间。该项目的调查人员还将与K-8教师合作，用让学生接触计算机科学基本概念和技能的材料来增强现有的STEM课程。这一点尤其重要，因为计算机科学概念现在是在全州范围内的标准化考试中进行评估的。为了探索IMC设计空间，器件级建模，电路/架构级建模，器件非理想性（例如，变化）分析，以及集成针对特定应用程序级工作负载的异构体系结构解决方案的方法都必须加以研究。在IMC空间中，（i）候选技术的数量很大并且不断变化，（ii）多个候选IMC电路和架构-例如，在阵列外围（CAP）、内容可寻址存储器（CAM）和交叉开关处的计算，（iii）IMC解决方案可能更容易受到设备变化/非理想性的影响，并且必须在应用级捕获这种影响，（iv）新兴技术使能的IMC解决方案可以与现有架构解决方案一起使用和/或用于各种异构设计中，以及（v）实际上存在可以考虑的无限数量的应用级映射/潜在算法改变。关于器件模型，存在对铁电器件的有意关注-即，前端制程硅铁电场效应晶体管、后端制程金属氧化物铁电场效应晶体管和多栅极铁电场效应晶体管-这是由于对该技术的兴趣不断增长以及需要考虑单片3D处理/存储器系统。 对于IMC电路/架构，该项目将为两种不同的内存计算“口味”扩展和开发建模/评估工具-（i）CAM（可以报告与给定查询最匹配的内存条目）和（ii）CAP。对于CAM，代表性的工作包括预测二进制、三进制、多级和模拟CAM阵列的品质因数（读/写能量和延迟等）。针对不同的匹配功能，用不同的非易失性存储器实现的设计。还将考虑确定最佳CAM阵列尺寸和其他设计参数。还将开发针对不同NVM的CAP设计的评估。对于应用程序，将评估基于MLPerf应用程序子集的IMC结构的解决方案。MLPerf代表了一个由人工智能领导者组成的联盟，他们已经为视觉、语言等方面的工作量做出了贡献。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。