III-V semiconductor nanowires: correlation of local electronic structure, conductivity, and carrier lifetime

III-V族半导体纳米线：局部电子结构、电导率和载流子寿命的相关性

• 批准号: 390247238
• 负责人: Professor Dr. Mario Dähne, since 5/2021
• 金额: --
• 依托单位: Institut dÉlectronique de Microélectronique et de Nanotechnologie (IEMN)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2018
• 资助国家: 德国
• 起止时间: 2017-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/390247238?language=en
• 关键词: III; semiconductor; nanowires; correlation; local

Semiconductor nanowires (NW) are promising building blocks of novel electronic and optoelectronic devices, with an exceptional wide range for tailoring electronic properties by size, geometry, and different crystallographic structures. Even crystallographic structures being not available as bulk materials can be produced. Hence, NWs are considered for many potential applications ranging from solar cells to nanoelectronics. However, many fundamental aspects remain to be elucidated. Two of them are particularly relevant: First, the NW geometry leads to a very high surface-to-volume ratio. Consequently, surface-induced effects, such as Fermi level pinning, play a large role for the properties of NWs and the functionality of devices based on them. Second, NWs may contain frequently polytype insertions, twin boundaries, and stacking faults in addition to intentionally inserted heterointerfaces. They affect the electronic properties, introduce band offsets, and hence influence the conductivity and carrier lifetimes. Therefore, the overall objective of this project is to investigate the electronic properties of sidewall surfaces, defects, and interfaces with atomic resolution, and correlate them with conductivity and carrier lifetimes of III-V semiconductor NWs.In particular, we plan to investigate in a first step (i) the possible Fermi level pinning, the energetic position, and its physical origin at the sidewall surfaces of different III-V material compositions and for different polytypes, (ii) the interface states, band alignments and offsets, as well as band gaps near heterointerfaces, (iii) the electronic properties of planar defects and polytype insertions, and (iv) the interaction of the surface Fermi level pinning with internal junctions, interfaces, and defects. In a second step, these properties will be correlated with the conductivity and carrier lifetimes of NWs. The main objectives are to elucidate, how an extrinsic surface pinning, interfaces as well as planar defects, and intentionally incorporated point defects affect conductivity and carrier lifetimes of NWs.

半导体纳米线（NW）是新型电子和光电器件的有前途的构建块，具有通过尺寸、几何形状和不同晶体结构定制电子性质的异常宽的范围。即使晶体结构不能作为块体材料，也可以生产。因此，纳米线被认为是从太阳能电池到纳米电子学的许多潜在应用。然而，许多基本方面仍有待阐明。其中两个是特别相关的：第一，NW几何形状导致非常高的表面积与体积比。因此，表面诱导效应，如费米能级钉扎，对纳米线的性质和基于它们的器件的功能起着很大的作用。第二，NW可能包含频繁的多型插入，孪晶边界和堆垛层错，除了有意插入的异质界面。它们影响电子性质，引入能带偏移，从而影响电导率和载流子寿命。因此，本项目的总体目标是以原子分辨率研究侧壁表面、缺陷和界面的电子特性，并将其与III-V族半导体纳米线的电导率和载流子寿命相关联。特别地，我们计划在第一步中研究（i）可能的费米能级钉扎，能量位置，以及其在不同III-V族材料成分的侧壁表面处的物理起源，以及对于不同的多型体，（ii）界面态、能带对准和偏移，以及异质界面附近的带隙，（iii）平面缺陷和多型插入的电子性质，以及（iv）表面费米能级钉扎与内部结、界面和缺陷的相互作用。在第二步中，这些属性将与纳米线的导电性和载流子寿命相关。的主要目标是阐明，如何一个外在的表面钉扎，接口以及平面缺陷，并有意纳入点缺陷影响导电性和载流子寿命的纳米线。