III-V semiconductor nanowires: correlation of local electronic structure, conductivity, and carrier lifetime

点击翻译按钮获取中文摘要

Semiconductor nanowires (NW) are promising building blocks of novel electronic and optoelectronic devices, with an exceptional wide range for tailoring electronic properties by size, geometry, and different crystallographic structures. Even crystallographic structures being not available as bulk materials can be produced. Hence, NWs are considered for many potential applications ranging from solar cells to nanoelectronics. However, many fundamental aspects remain to be elucidated. Two of them are particularly relevant: First, the NW geometry leads to a very high surface-to-volume ratio. Consequently, surface-induced effects, such as Fermi level pinning, play a large role for the properties of NWs and the functionality of devices based on them. Second, NWs may contain frequently polytype insertions, twin boundaries, and stacking faults in addition to intentionally inserted heterointerfaces. They affect the electronic properties, introduce band offsets, and hence influence the conductivity and carrier lifetimes. Therefore, the overall objective of this project is to investigate the electronic properties of sidewall surfaces, defects, and interfaces with atomic resolution, and correlate them with conductivity and carrier lifetimes of III-V semiconductor NWs.In particular, we plan to investigate in a first step (i) the possible Fermi level pinning, the energetic position, and its physical origin at the sidewall surfaces of different III-V material compositions and for different polytypes, (ii) the interface states, band alignments and offsets, as well as band gaps near heterointerfaces, (iii) the electronic properties of planar defects and polytype insertions, and (iv) the interaction of the surface Fermi level pinning with internal junctions, interfaces, and defects. In a second step, these properties will be correlated with the conductivity and carrier lifetimes of NWs. The main objectives are to elucidate, how an extrinsic surface pinning, interfaces as well as planar defects, and intentionally incorporated point defects affect conductivity and carrier lifetimes of NWs.