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Development of an Integrated Analog-Digital CAD System

集成模拟数字 CAD 系统的开发

基本信息

批准号：
01850076
负责人：
TAMARU Keikichi
金额：
$ 9.47万
依托单位：
Kyoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research
财政年份：
1989
资助国家：
日本
起止时间：
1989 至 1991
项目状态：
已结题

项目摘要

The purpose of this research project is the development of an integrated Analog-Digital CAD system that supports circuit and layout design for Analog and mixed Analog-Digital LSIS. The results of the project are summarized as follows.1. We have developed a symbolic layout system. The system allows a designer to define new layout patterns of any devices which are tailored according to his need. Newly established compaction algorithm enables the system to compact Analog layout under symmetry constraints.2. We have developed a system for module generator development. A method for generating layout description from a graphically designed layout has been devised. With the use of the system, a designer can develop a module generator using a graphic editor, which is more user-friendly than conventional programming.3. We have established an automatic placement method for building blocks and analog components. The placement algorithm is a branch-and-bound search for an optimal solution from all the possible placements.4. We have developed an automatic design system for CMOS operational amplifier-amps. A knowledge-based process followed by a numerical optimization searches for a good design effectively in a vast solution space. During device sizing, layout information are back-annotated "on the fly", thus circuit performance is optimized considering the effect of layout parasitics precisely.5. We have developed a layout-driven logic synthesis system. Terminal positions of logic gates are taken into account in a logic restructuring process, which consideration will reduce interconnection length of a final circuit. The output of the system is a standard cell layout.6. We have considered a method of evaluation for CAD tools, and proposed a comprehensive set of benchmarks which is applicable to CAD tools for any design levels.In this project we mainly focused on a synthesis phase of LSI design. Our further research will include verification and test of LSIs.

本研究计画的目的是开发一个整合类比数位CAD系统，以支援类比及类比数位混合型大规模集成电路的电路与布局设计。本项目的研究成果总结如下：1.我们开发了一个符号布局系统。该系统允许设计者定义新的布局模式的任何设备是根据他的需要定制。新建立的压缩算法使系统能够在对称性约束下压缩模拟版图.我们开发了一个模块生成器开发系统。设计了一种从图形化设计的版图生成版图描述的方法。使用该系统，设计人员可以使用图形编辑器开发模块生成器，这比传统的编程更加用户友好.我们已经建立了一个自动布局方法的积木和模拟元件。布局算法是从所有可能的布局中寻找最优解的分支定界搜索.我们开发了一个CMOS运算放大器的自动设计系统。一个基于知识的过程，其次是数值优化搜索一个良好的设计有效地在一个巨大的解决方案空间。在器件尺寸调整过程中，“动态”对布局信息进行反向注释，从而精确考虑布局寄生效应的影响来优化电路性能。5.我们开发了一个版图驱动的逻辑综合系统。在逻辑重构过程中考虑逻辑门的端子位置，这一考虑将减少最终电路的互连长度。该系统的输出是一个标准的单元布局。我们考虑了一种评估CAD工具的方法，并提出了一套全面的基准，这是适用于任何设计水平的CAD工具。在这个项目中，我们主要集中在LSI设计的综合阶段。我们的进一步研究将包括验证和测试LSI。