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Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.

功能存储器型并行处理器架构及其大规模并行算法的研究。

基本信息

批准号：
02452160
负责人：
TAMARU Keikichi
金额：
$ 4.29万
依托单位：
KYOTO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1990
资助国家：
日本
起止时间：
1990 至 1992
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-02452160/
关键词：
Functional Memory Type Parallel Processor Architecture FMPP Content Addressable Memory Functional Memory Massively Parallel Algorithm SIMD Massively Parallel Computation Massively Parallel Processing 機能メモリ型並列プロセサ超並列計算機アーキテクチャ計算機アーキテク

项目摘要

We have made an in-depth study on a parallel processor architecture called FMPP (Functional Memory Type Parallel Processor Architecture) and massively parallel algorithms on FMPP. Results are summarized as follows.(1) Studies on Massively Parallel Computation Capability of FMPP: Introduction of some computational power inside memory circuits enables FMPP to realize a highly parallel computation in the memory circuits.(2) Studies on Integrated Circuit Technology for FMPP: Based on the recent technology trend of a CAM LSI which is the principal component of FMPP, Integration scale of CAM LSIs in 0.8 mum CMOS technology is predicted to be 100 Kbit with SRAM cells and 400 Kbit with DRAM cells. In 0.5 mum technology, it will reach 1 Mbit with DRAM cells(3) Studies on a new FMPP architecture: A new architecture of FMPP called bit-parallel block-parallel (BPBP) FMPP has been proposed. So far, a bit-serial word-parallel (BSWP) implementation based on a CAM is mainly considered as one of promising architectures of FMPP. The BSWP FMPP achieves massively parallel computation in a reasonable hardware amount. It however does not allow operations between two words, which restriction limits the the applicability of the BSWP FMPP. The BPBP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words call a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and in suitable for various applications.(4) Studies on massively parallel algorithms for FMPP: We have developed various parallel algorithms for FMPP which has a highly parallel SIMD computation scheme. The targets of the algorithms include pattern matching, the shortest path problem, logic simulation, intersection calculation of lines, ray tracing, and neural network simulation.

本文对一种名为FMPP （Functional Memory Type parallel processor architecture）的并行处理器架构和基于FMPP的大规模并行算法进行了深入的研究。结果总结如下。(1) FMPP大规模并行计算能力的研究：在内存电路中引入一定的计算能力，使FMPP能够在内存电路中实现高度并行计算。(2) FMPP集成电路技术的研究：基于FMPP的主要组件CAM LSI的最新技术趋势，预测在0.8 m CMOS技术下，CAM LSI的集成规模为100 Kbit （SRAM单元）和400 Kbit （DRAM单元）。(3)一种新的FMPP体系结构的研究：提出了一种新的FMPP体系结构，称为位并行块并行（BPBP） FMPP。目前，基于CAM的位串行字并行（BSWP）实现被认为是最有前途的FMPP架构之一。BSWP FMPP在合理的硬件数量下实现了大规模并行计算。然而，它不允许两个词之间的操作，这限制了BSWP FMPP的适用性。BPBP被设计用于对两个单词执行逻辑和算术运算。这些操作在每组称为块的单词上同时执行。BPBP FMPP在保持BSWP高集成度的同时实现了高性能，适用于各种应用。(4) FMPP的大规模并行算法研究：我们开发了各种FMPP的并行算法，这些算法具有高度并行的SIMD计算方案。这些算法的目标包括模式匹配、最短路径问题、逻辑仿真、直线相交计算、光线追踪和神经网络仿真。