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Development of a Computer Specific to LSI Geometrical Processing

Development of a Computer Specific to LSI Geometrical Processing
LSI几何处理专用计算机的研制
批准号:
04555078
负责人:
TAMARU Keikichi
金额:
$10.18万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
财政年份:
1992
资助国家:
日本
项目状态:
已结题
起止时间:
1992 至 1994

项目摘要

项目成果

TAMARU Keikichi的其他基金

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中文摘要
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英文摘要
The objective of this research is that we should develop a specific computer which performs geometrical-figure processing very rapidly. The geometrical-figure processing is the primitive function in the current LSI design. It comprises logical, topological and geometrical operations and also area/length calculation.This research aimed to dissolve the bottle-neck in the current LSI design process by that specific computer.The results of this research are as follows1.Acceleration of parallel processing in LSI design rule check (DRC)2.Development of a computer system specific to LSI DRC3.A method of DRC by functional partitioning.4.Development of a functional memory type parallel processor.We constructed a computer system to evaluate the above results. A host computer which controls all processor elements (called workers) is a standard engineering work station using 68040 processors. We developed four brand-new workers. The worker performs data input and output simultaneously using two-port memory modules. The DRC processing unit in the worker is a single-board computer which comprises a CPU called M32/100. And also we developed software packages which control the system and performs DRC.This system with two workers performs DRC twice faster than that with a single worker.
期刊论文(12)
专著(0)
科研奖励(0)
会议论文
K.Tamaru: "The Trend of Functional Memory Development" IEICE Trans.Electron.E76-C. 1545-1554 (1993)
K.Tamaru:“功能存储器发展趋势”IEICE Trans.Electron.E76-C。
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通讯作者:
K.Kobayashi: ""A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture"" IEICE Trans.Electron.Vol.E76-C,No.7. 1151-1158 (1993)
K.Kobayashi:“一种位并行块并行功能存储器型并行处理器架构””IEICE Trans.Electron.Vol.E76-C,No.7。
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通讯作者:
K.Koboyashi: "A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture" IEICE Trans.Electron.E76-C. 1151-1158 (1993)
K.Koboyashi:“一种位并行块并行功能存储器类型并行处理器架构”IEICE Trans.Electron.E76-C。
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通讯作者:
田丸 啓吉: "“新しい機能メモリー演算機能を持つメモリー"" 1994年電子情報通信学会秋季全国大会講演論文集. No.GC-2-6. 261-262 (1994)
Keikichi Tamaru:“‘具有新的功能性存储器算术功能的存储器’”1994 年秋季全国电子、信息和通信工程师学会会议记录,No.GC-2-6 (1994)。
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12
    Development of a Computing System by a Functional Memory Type Parallel Processor.
    • 批准号:
      07558039
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $5.95万
    • 财政年份:
      1995
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Effective Design Methodology for Analog LSIs that Acquires and Reuses Design
    • 批准号:
      05452197
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $4.61万
    • 财政年份:
      1993
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.
    • 批准号:
      02452160
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $4.29万
    • 财政年份:
      1990
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Development of an Integrated Analog-Digital CAD System
    • 批准号:
      01850076
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research
    • 资助金额:
      $9.47万
    • 财政年份:
      1989
    • 负责人:
      TAMARU Keikichi
    • 依托单位: