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Studies on a Hierarchical CAD System for Analog LSIs

Studies on a Hierarchical CAD System for Analog LSIs
模拟LSI分层CAD系统的研究
批准号:
62460127
负责人:
TAMARU Keikichi
金额:
$4.99万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1987
资助国家:
日本
项目状态:
已结题
起止时间:
1987 至 1988

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项目成果

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中文摘要
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英文摘要
With rapid progress in integrated circuit technologies, there is a growing demand for analog LSIs and mixed analog/digital LSIs. Existing CAD systems for LSI, however, mainly put their target on handle digital circuits. Few system can treats analog circuits, which makes the design cost of full custom analog circuits prohibitively high. Therefore, it is strongly required to establish the design methodology and CAD tool for analog circuits.In this research project, we have investigated a CAD system for analog LSIs which has been constructed on the same framework as CAD systems for digital LSIs. Special interests have been put on the following points: how to introduce the concept of hierarchical design, how to manage the correspondence between circuit and layout, how to automate the optimization of various design parameters, and how to describe the design data for analog circuits. Brief descriptions of the obtained results are shown below.1. Studies on an automatic synthesis system for analog circuits: A method has been proposed that utilizes a non-linear optimization technique for the determination of design parameters in analog circuits. This method is applied to an automatic design system for operational amplifiers which generates layout of an optimally designed circuit from its performance specifications.2. Development of a hierarchical symbolic layout design system: A new layout design methodology using data description with correspondence between circuit and layout has been proposed. Based on the methodology, we have developed a symbolic layout design system which adopts newly developed hierarchical compaction method.3. Studies on design language for analog circuits: To establish a design language for mixed analog/digital LSI, we participate an activity of standardization of LSI design language for JIS. By the above research activities, we obtained fundamental techniques for analog LSI CAD systems.
期刊论文(14)
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会议论文
Hidetoshi,Onodera: Trans.IEICE Japan. Eー71. 947-949 (1988)
小野寺英俊:Trans.IEICE 日本。 947-949 (1988)
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通讯作者:
小野寺秀俊: 電子情報通信学会論文誌. J72-A. 105-113 (1989)
Hidetoshi Onodera:电子、信息和通信工程师学会汇刊 J72-A(1989)。
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通讯作者:
Ryosuke,Okuda: "A Layout Design Methodology Using Data Description with Correspondence between Circuit and Layout" Trans. IEICE Japan. J71-A. 2156-2162 (1988)
Ryosuke,Okuda:“使用数据描述与电路和布局之间的对应关系的布局设计方法”Trans。
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通讯作者:
Hidetoshi,Onodera: "Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method" Trans. IEICE Japan. E-71. 947-949 (1988)
Hidetoshi,Onodera:“使用非线性优化方法生成 CMOS 运算放大器的模块”Trans。
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10
    Development of a Computing System by a Functional Memory Type Parallel Processor.
    • 批准号:
      07558039
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $5.95万
    • 财政年份:
      1995
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Effective Design Methodology for Analog LSIs that Acquires and Reuses Design
    • 批准号:
      05452197
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $4.61万
    • 财政年份:
      1993
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Development of a Computer Specific to LSI Geometrical Processing
    • 批准号:
      04555078
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research (B)
    • 资助金额:
      $10.18万
    • 财政年份:
      1992
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.
    • 批准号:
      02452160
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $4.29万
    • 财政年份:
      1990
    • 负责人:
      TAMARU Keikichi
    • 依托单位:
    海外基金