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Studies on a Hierarchical CAD System for Analog LSIs

模拟LSI分层CAD系统的研究

基本信息

批准号：
62460127
负责人：
TAMARU Keikichi
金额：
$ 4.99万
依托单位：
Kyoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1987
资助国家：
日本
起止时间：
1987 至 1988
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-62460127/
关键词：
Analog LSI CAD System Hierarchical Design Symbolic Layout Layout Editor Methodology of Block Placement Compaction オペアンプの自動設計アナログ回路 LSI レイアウト回路解析回路記述自動設計デバイスシミュレータ

项目摘要

With rapid progress in integrated circuit technologies, there is a growing demand for analog LSIs and mixed analog/digital LSIs. Existing CAD systems for LSI, however, mainly put their target on handle digital circuits. Few system can treats analog circuits, which makes the design cost of full custom analog circuits prohibitively high. Therefore, it is strongly required to establish the design methodology and CAD tool for analog circuits.In this research project, we have investigated a CAD system for analog LSIs which has been constructed on the same framework as CAD systems for digital LSIs. Special interests have been put on the following points: how to introduce the concept of hierarchical design, how to manage the correspondence between circuit and layout, how to automate the optimization of various design parameters, and how to describe the design data for analog circuits. Brief descriptions of the obtained results are shown below.1. Studies on an automatic synthesis system for analog circuits: A method has been proposed that utilizes a non-linear optimization technique for the determination of design parameters in analog circuits. This method is applied to an automatic design system for operational amplifiers which generates layout of an optimally designed circuit from its performance specifications.2. Development of a hierarchical symbolic layout design system: A new layout design methodology using data description with correspondence between circuit and layout has been proposed. Based on the methodology, we have developed a symbolic layout design system which adopts newly developed hierarchical compaction method.3. Studies on design language for analog circuits: To establish a design language for mixed analog/digital LSI, we participate an activity of standardization of LSI design language for JIS. By the above research activities, we obtained fundamental techniques for analog LSI CAD systems.

随着集成电路技术的快速发展，对模拟lsi和模拟/数字混合lsi的需求不断增长。然而，现有的大规模集成电路CAD系统主要把目标放在处理数字电路上。很少有系统可以处理模拟电路，这使得全定制模拟电路的设计成本高得令人望而却步。因此，迫切需要建立模拟电路的设计方法和CAD工具。在这个研究项目中，我们研究了一个模拟lsi的CAD系统，该系统与数字lsi的CAD系统建立在相同的框架上。特别关注以下几点：如何引入分层设计的概念，如何管理电路与布局之间的对应关系，如何自动优化各种设计参数，以及如何描述模拟电路的设计数据。所得结果的简要说明如下。模拟电路自动合成系统的研究：提出了一种利用非线性优化技术确定模拟电路设计参数的方法。将该方法应用于运算放大器的自动设计系统中，该系统根据运算放大器的性能指标生成最优设计电路的版图。分层符号布局设计系统的开发：提出了一种利用电路与布局对应的数据描述进行布局设计的新方法。在此基础上，我们开发了一种采用分层压缩法的符号布局设计系统。模拟电路的设计语言研究：为了建立模拟/数字混合LSI的设计语言，我们参与了JIS的LSI设计语言标准化活动。通过上述研究活动，我们获得了模拟LSI CAD系统的基本技术。