phySicAlly secUre reconfiguraBlE platfoRm (SAUBER)

在日益增长的数字世界中，日常生活的许多方面完全由信息技术基础设施完成，他们对安全的担忧比以往任何时候都要大。一方面软件变得越来越安全，另一方面硬件变得越来越容易，硬件成为系统安全的阿喀琉斯之踵。在当今复杂的片上系统（soc）中，以现场可编程门阵列（FPGA）形式的可重构结构因其快速上市、灵活性和可更新性而发挥着重要作用。fpga在许多安全平台上也很有前途，因为它们允许对硬件和系统进行“安全补丁”，就像在软件中通常做的那样。尽管FPGA在安全应用方面有这样的前景，但由于现有的商用可重构技术并不是为安全应用而设计的，因此FPGA结构仍然有许多安全问题需要解决。在FPGA平台上，由于高面积、低吞吐量、高功耗、高延迟等原因，目前已知的对抗物理攻击的方法在应用中存在挑战。这种安全方案到FPGA的实现和映射是“ad hoc”的，这意味着对于每一个加密算法和每一个设计架构，对策都应该重新调整。此外，现有的FPGA技术容易受到许多安全攻击和侧信道分析，甚至使攻击者能够远程攻击系统。该项目的主要目标是设计一个安全的可重构平台（SAUBER），该平台可以抵御各种恶意物理攻击，并可以作为soc中的信任中心，以实现加密算法和其他高度安全的功能。新平台将提供强大的保护，防止侧信道分析攻击、故障注入攻击、热攻击、电源噪声攻击，同时启用可调整的安全原语，例如PRNG，这是针对物理攻击的算法对策所必需的。我们将研究如何采用和重新设计目前可用的基于asic的隐藏对策，以便在可重构平台中实现它们将导致对物理攻击的强大保护。我们将在现有开源FPGA映射工具的基础上，设计安全可重构结构，开发安全映射工具链，自动将用户应用映射到该平台，并以系统和自动化的方式嵌入安全特性。

In the growing digital world, where many aspects of daily life are solely performed by the information technology infrastructure, their security concerns are greater than ever before. With software becoming more secure on one hand, and compromising hardware becoming easier on the other hand, the hardware becomes the Achilles heel for the system security. In complex systems on chip (SoCs) of today, the reconfigurable fabric, in the form of field programmable gate array (FPGA), plays an important role due to its rapid time to market, flexibility, and updatability. FPGAs are also very promising for many secure platforms, since they allow “security patches” to the hardware and the system, as it is normally done in software. Despite such promising prospects of FPGAs for secure applications, there are still many security issues to be resolved for the FPGA fabric since the existing commercially-available reconfigurable technology is not made for secure applications. There exist challenges in applying the currently-known countermeasures to physical attacks in FPGA platforms, due to high area, low throughput, high power/energy, high latency, etc. The implementation and mapping of such security schemes to the FPGA is “ad hoc”, meaning for every cryptographic algorithm and every design architecture, the countermeasures should be readjusted. In addition, the existing FPGA technology is vulnerable to many security attacks and side-channel analysis, even enabling adversaries to attack the system remotely.The main objective of this project is to design a secure reconfigurable platform (SAUBER), which is resilient to various malicious physical attacks and can act as the center of trust in SoCs, in order to implement cryptographic algorithms and other highly secure functions. The new platform would provide strong protection against side-channel analysis attacks, fault-injection attacks, thermal attacks, power supply noise attacks and at the same time enable adjustable security primitives, e.g., PRNG, necessary for algorithmic countermeasures against physical attacks. We will investigate how to adopt and re-design currently available ASIC-based hiding countermeasures so that their realization in a reconfigurable platform would lead to strong protection against physical attacks. We will design the secure reconfigurable fabric and develop the secure mapping toolchain, on top of existing open source FPGA mapping tools, to automatically map user applications to this platform and embed security features in a systematic and automated manner.