Fundamental study on design for testing of multi-layer structure VLSIs

多层结构VLSI测试设计基础研究

• 批准号: 10450137
• 负责人: FUJIOKA Hiromu
• 金额: $ 6.08万
• 依托单位: Osaka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B).
• 财政年份: 1998
• 资助国家: 日本
• 起止时间: 1998 至 2000
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-10450137/
• 关键词: design for testability; LSI with multi-layer structure; test pad; current testing; current test point; fault localization; EB testability; VLSI; パーティクル

The electron beam (EB) test system has been widely used to measure internal signal behavior in LSI.However, with an advance in the LSI manufacturing, there has been a tendency to design an LSI with a multi-layer structure. This multi-layer structure causes the decrease in testability of the EB test system.In order to alleviate the difficulties in testing LSIs, we develop the test pad introduction tool and propose the current test points that complement the voltage test points.The former test pad means the electrode on the uppermost layer connected to the electrode on the lower layer to be measured. We designed the test pad cell with area as small as possible to be probed with an EB tester. Then the number and the insertion positions of test pads are determined to narrow down the faulty area size to the specified number of primitive cells. By applying the test pad introduction tool to the self-made 8-bit microprocessor LSI, the improvement in testability of the EB test system and the performance deterioration such as the delay time were examined. Results shows that the faulty area size of about 1300 was improved to 100 by introducing 50 test pads and the performance deterioration could be neglected.The latter current test point passes an electric current with a prescribed value when the control signal is set at a test mode. By checking whether the total power supply current is equal to the sum of the prescribed current values or not, we know the device under test (DUT) is faulty or not. When the control signal is set at a normal mode, the DUT performs normal operations. We established the design method of current test point cells under various constraints such as process variations.

电子束（EB）测试系统已被广泛用于测量LSI中的内部信号行为。然而，随着LSI制造的进步，已出现设计具有多层结构的LSI的趋势。这种多层结构导致电子束测试系统的可测性下降，为了缓解LSI测试的困难，我们开发了测试焊盘引入工具，提出了电流测试点与电压测试点的互补，前者是指最上层的电极与下层的待测电极相连。我们设计的测试垫单元的面积尽可能小，可以用电子束测试仪进行探测。然后，确定测试焊盘的数目和插入位置，以将故障区域尺寸缩小到指定的原始单元数目。通过将测试焊盘引入工具应用于自制的8位微处理器LSI，检查了EB测试系统的可测试性的改善和诸如延迟时间的性能劣化。结果表明，通过引入50个测试焊盘，故障区域大小从1300左右提高到100左右，性能下降可以忽略不计，当控制信号设置在测试模式时，后一个电流测试点通过规定值的电流。通过检查总电源电流是否等于规定的电流值之和，我们可以知道被测设备（DUT）是否有故障。当控制信号被设置为正常模式时，DUT执行正常操作。建立了在工艺变化等各种约束条件下电流测试点单元的设计方法。

项目成果

K.Miura: "Intelligent EB Test System for Automatic VLSI Fault Tracing"Proc.8th IEEE Asian Test Symposium. 335-340 (1999)

K.Miura：“用于自动 VLSI 故障跟踪的智能 EB 测试系统”Proc.8th IEEE 亚洲测试研讨会。

S.Yagyu: "Test Pad Introduction Tool for EB Testability"Proc.Symposium on LSI Testing. 7-12 (1999)

S.Yagyu：“用于 EB 可测试性的测试垫介绍工具”Proc.LSI 测试研讨会。

K.Miura: "Automatic EB Fault-Tracing System Using Fuzzy-Logic Approach"11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis. 1377-1382 (2000)

K.Miura：“使用模糊逻辑方法的自动 EB 故障跟踪系统”第 11 届欧洲电子器件可靠性、故障物理与分析研讨会。

T.Nagai: "Dccision of the Priority in the Test Pad Arrangement for EB Testability by Layout Analysis"Proc.Symposium on LSI Testing. 128-133 (1998)

T.Nagai：“通过布局分析确定 EB 可测试性的测试焊盘排列的优先级”Proc.LSI 测试研讨会。

H.Yamazaki: "Internal Current Test Point Introduction to Improve VLSI Testability"Proc.Symposium on LSI Testing. 13-18 (1999)

H.Yamazaki：“内部电流测试点介绍以提高 VLSI 可测试性”Proc.LSI 测试研讨会。