Automatic hierarchical tracing of VLSI transistor-level performance faults with CAD-linked electron beam test system from CAD layout data

为了实现只需要CAD版图数据的高效故障追踪，我们首先分析了国际上广泛使用的GDS II格式的CAD版图数据的层次结构。布局分析使我们可以构建一棵细胞树，其中树的组件单元从树的底层到树的顶层被分为叶单元、基元单元和块单元。接下来，我们提出了一种用于树中高层的分层故障跟踪算法。该算法允许我们通过双向母线跟踪VLSI中的故障，而不依赖于电路块功能，在电路块功能中，通过使用EB测试仪采集的波形来判断信号流的方向。此外，我们还提出了适用于树中较低层的故障跟踪算法。该方法通过利用从CAD布局数据生成的用于基元单元和块单元的布局字典来跟踪故障。版图词典不仅包含版图，还包含单元名称、电路功能、边界框、输入和输出端子的位置以及触点的位置。在输入中，指定了控制线。我们现在正在使用提出的故障跟踪算法构建一个自动故障跟踪系统。系统硬件由EB测试系统、LSI测试系统、服务器计算机和上位机组成，它们都是基于以太网的网络所喜欢的。系统软件目前正在通过集成故障跟踪算法、波形测量的最佳探测点选择、DUT互连图案与CAD布局匹配、波形比较、EB测试仪控制和LSI测试仪控制等程序来实现。现在，我们将该测试系统应用于自制的8位微处理器LSI(VDEC 1996原型制造)，以验证其有效性。

To realize the efficient fault tracing that requires only CAD layout data, we have first analyzed the hierarchical structure of the CAD layout data with the GDS II format that is widely used in the world. The layout analysis allows us to construct a cell tree where tree component cells are classified into leaf cells, primitive cells and block cells from the bottom level to the top in the tree. Next, we have proposed the hierarchical fault-tracing algorithm that is used for high levels in the tree. The algorithm allows us to trace a fault in VLSIs with bi-directional busses independently of circuit block functions where the direction of the signal flow is judged by using waveforms acquired by an EB tester. Moreover, we have proposed the fault-tracing algorithm that is used for lower levels in the tree. The method traces a fault by utilizing a layout dictionary for primitive cells and for block cells that is generated from a CAD layout data. The layout dictionary contains not only the layouts, but also cell name, its circuit function, its bounding box, the position of the input and output terminals, and the position of contacts. Among the inputs, the control lines are specified. We are now constructing an automatic fault tracing system using the proposed fault tracing algorithms. The system hardware consists of an EB test system, an LSI test system, a server computer, and a host computer which are liked by an Ethernet-based network. The system software is now implementing by integrating the programs for the fault tracing algorithms, the optimal probing point selection for waveform measurements, matching of DUT interconnection pattern with CAD layout, waveform comparison, control of the EB tester, and control of the LSI tester. We are now applying the test system to a self-made-8-bit microprocessor LSI (VDEC 1996 prototype manufacturing) to show its validity.