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Automatic hierarchical tracing of VLSI transistor-level performance faults with CAD-linked electron beam test system from CAD layout data

使用 CAD 链接电子束测试系统根据 CAD 布局数据自动分层跟踪 VLSI 晶体管级性能故障

基本信息

批准号：
08455164
负责人：
FUJIOKA Hiromu
金额：
$ 3.07万
依托单位：
Osaka University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1996
资助国家：
日本
起止时间：
1996 至 1997
项目状态：
已结题

项目摘要

To realize the efficient fault tracing that requires only CAD layout data, we have first analyzed the hierarchical structure of the CAD layout data with the GDS II format that is widely used in the world. The layout analysis allows us to construct a cell tree where tree component cells are classified into leaf cells, primitive cells and block cells from the bottom level to the top in the tree. Next, we have proposed the hierarchical fault-tracing algorithm that is used for high levels in the tree. The algorithm allows us to trace a fault in VLSIs with bi-directional busses independently of circuit block functions where the direction of the signal flow is judged by using waveforms acquired by an EB tester. Moreover, we have proposed the fault-tracing algorithm that is used for lower levels in the tree. The method traces a fault by utilizing a layout dictionary for primitive cells and for block cells that is generated from a CAD layout data. The layout dictionary contains not only the layouts, but also cell name, its circuit function, its bounding box, the position of the input and output terminals, and the position of contacts. Among the inputs, the control lines are specified. We are now constructing an automatic fault tracing system using the proposed fault tracing algorithms. The system hardware consists of an EB test system, an LSI test system, a server computer, and a host computer which are liked by an Ethernet-based network. The system software is now implementing by integrating the programs for the fault tracing algorithms, the optimal probing point selection for waveform measurements, matching of DUT interconnection pattern with CAD layout, waveform comparison, control of the EB tester, and control of the LSI tester. We are now applying the test system to a self-made-8-bit microprocessor LSI (VDEC 1996 prototype manufacturing) to show its validity.

为了实现仅需要CAD布局数据的高效故障追踪，我们首先分析了国际上广泛使用的GDS II格式的CAD布局数据的层次结构。布局分析允许我们构建一个单元树，其中树组件单元从树的底层到顶部被分为叶单元、原始单元和块单元。接下来，我们提出了用于树中高层的分层故障跟踪算法。该算法使我们能够独立于电路块功能来跟踪具有双向总线的 VLSI 中的故障，其中信号流的方向是通过使用 EB 测试仪采集的波形来判断的。此外，我们还提出了用于树中较低级别的故障跟踪算法。该方法通过利用从CAD布局数据生成的图元单元和块单元的布局字典来追踪故障。布局字典不仅包含布局，还包含单元名称、其电路功能、其边界框、输入和输出端子的位置以及触点的位置。在输入中，指定了控制线。我们现在正在使用所提出的故障追踪算法构建自动故障追踪系统。系统硬件由EB测试系统、LSI测试系统、服务器计算机和主机组成，采用基于以太网的网络。该系统软件目前正在通过集成故障追踪算法、波形测量的最佳探测点选择、DUT互连模式与CAD布局的匹配、波形比较、EB测试仪的控制以及LSI测试仪的控制等程序来实现。我们现在将该测试系统应用到自制的8位微处理器LSI（VDEC 1996年样机制造）上以验证其有效性。