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A Research on Hierarchical Processor Architecture

分层处理器体系结构的研究

基本信息

批准号：
10480062
负责人：
SHIBAYAMA Kiyoshi
金额：
$ 5.89万
依托单位：
Kyoto Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B).
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

项目摘要

Today's computer system consists mainly of a processor, a memory module, and an I/O (communication) subsystem as hardware resources, connected with each other.A processor, which is a kernel processing the information has the two ways for acquiring data to operate. One is a memory access for loadins/storing data from/to memory of an internal resource on a computer system, and the other is a communication for sending/receiving data from/to the other external hardware. The inter-processor communication is an essential faculty to develop a parallel computer system, which is constructed with a number of processors connected with an interconnection network.A latency of the memory access and an inter-processor communication becomes a major factor of disturbing the improvement of total performance of computer systems. As the operating frequuency of microprocessors have highly increased, the relative cost of memory accesses has increased. On the other hand, although the recent high-speed network hardware enhances the data transfer rate in electric level, a large communication overhead in both of software and hardware, except the data transfer itself, is still disturbing the performance improvement of communications. Considering these states, we need to reconstruct the processor-memory architecture by investigating the optimal trade-off point among processor, memory, and communication. This research presents hierarchical processor architecture for high-speed memory access and inter-processor communication with two novel schemes.

当今的计算机系统主要由处理器、存储模块和I/O（通信）子系统作为硬件资源相互连接而成，处理器作为处理信息的核心，有两种获取数据的方式进行操作。一种是用于从计算机系统上的内部资源的存储器加载数据/将数据存储到计算机系统上的内部资源的存储器的存储器访问，另一种是用于从其他外部硬件发送数据/将数据接收到其他外部硬件的通信。处理器间通信是开发并行计算机系统的基本能力，该并行计算机系统由通过互连网络连接的多个处理器构成，存储器访问和处理器间通信的延迟成为干扰计算机系统总体性能提高的主要因素。随着微处理器的操作频率的高度增加，存储器访问的相对成本也增加了。另一方面，虽然最近的高速网络硬件在电子水平上提高了数据传输速率，但是除了数据传输本身之外，软件和硬件中的大的通信开销仍然干扰通信性能的提高。考虑到这些状态，我们需要通过研究处理器、存储器和通信之间的最佳折衷点来重构处理器-存储器架构。本研究提出两种新颖的架构，以提供阶层式的处理器架构来进行高速记忆体存取与处理器间的通讯。