A Research on Hierarchical Processor Architecture

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Today's computer system consists mainly of a processor, a memory module, and an I/O (communication) subsystem as hardware resources, connected with each other.A processor, which is a kernel processing the information has the two ways for acquiring data to operate. One is a memory access for loadins/storing data from/to memory of an internal resource on a computer system, and the other is a communication for sending/receiving data from/to the other external hardware. The inter-processor communication is an essential faculty to develop a parallel computer system, which is constructed with a number of processors connected with an interconnection network.A latency of the memory access and an inter-processor communication becomes a major factor of disturbing the improvement of total performance of computer systems. As the operating frequuency of microprocessors have highly increased, the relative cost of memory accesses has increased. On the other hand, although the recent high-speed network hardware enhances the data transfer rate in electric level, a large communication overhead in both of software and hardware, except the data transfer itself, is still disturbing the performance improvement of communications. Considering these states, we need to reconstruct the processor-memory architecture by investigating the optimal trade-off point among processor, memory, and communication. This research presents hierarchical processor architecture for high-speed memory access and inter-processor communication with two novel schemes.